X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Fpxa%2Fpxafb.c;h=0ee6a75319cdc83793146f7921c32ad48baa7b0a;hb=14d0a02a168b36e87665b8d7f42fa3e88263d26d;hp=d56c5f099f09155c7f3d03361b12dffe91428ad5;hpb=84ad688473bec2875e171b71040eb9e033c6c206;p=u-boot

diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c
index d56c5f099f..0ee6a75319 100644
--- a/arch/arm/cpu/pxa/pxafb.c
+++ b/arch/arm/cpu/pxa/pxafb.c
@@ -112,6 +112,39 @@ vidinfo_t panel_info = {
 	vl_efw:		0,
 };
 #endif /* CONFIG_SHARP_LM8V31 */
+/*----------------------------------------------------------------------*/
+#ifdef CONFIG_VOIPAC_LCD
+
+# define LCD_BPP	LCD_COLOR8
+# define LCD_INVERT_COLORS
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0	0x043008f8
+# define REG_LCCR3	0x0340FF08
+
+vidinfo_t panel_info = {
+	vl_col:		640,
+	vl_row:		480,
+	vl_width:	157,
+	vl_height:	118,
+	vl_clkp:	CONFIG_SYS_HIGH,
+	vl_oep:		CONFIG_SYS_HIGH,
+	vl_hsp:		CONFIG_SYS_HIGH,
+	vl_vsp:		CONFIG_SYS_HIGH,
+	vl_dp:		CONFIG_SYS_HIGH,
+	vl_bpix:	LCD_BPP,
+	vl_lbw:		0,
+	vl_splt:	1,
+	vl_clor:	1,
+	vl_tft:		1,
+	vl_hpw:		32,
+	vl_blw:		144,
+	vl_elw:		32,
+	vl_vpw:		2,
+	vl_bfw:		13,
+	vl_efw:		30,
+};
+#endif /* CONFIG_VOIPAC_LCD */
 
 /*----------------------------------------------------------------------*/
 #ifdef CONFIG_HITACHI_SX14
@@ -146,6 +179,40 @@ vidinfo_t panel_info = {
 };
 #endif /* CONFIG_HITACHI_SX14 */
 
+/*----------------------------------------------------------------------*/
+#ifdef CONFIG_LMS283GF05
+
+# define LCD_BPP	LCD_COLOR8
+/*# define LCD_INVERT_COLORS*/
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0	0x043008f8
+# define REG_LCCR3	0x03b00009
+
+vidinfo_t panel_info = {
+	vl_col:		240,
+	vl_row:		320,
+	vl_width:	240,
+	vl_height:	320,
+	vl_clkp:	CONFIG_SYS_HIGH,
+	vl_oep:		CONFIG_SYS_LOW,
+	vl_hsp:		CONFIG_SYS_LOW,
+	vl_vsp:		CONFIG_SYS_LOW,
+	vl_dp:		CONFIG_SYS_HIGH,
+	vl_bpix:	LCD_BPP,
+	vl_lbw:		0,
+	vl_splt:	1,
+	vl_clor:	1,
+	vl_tft:		1,
+	vl_hpw:		4,
+	vl_blw:		4,
+	vl_elw:		8,
+	vl_vpw:		4,
+	vl_bfw:		4,
+	vl_efw:		8,
+};
+#endif /* CONFIG_LMS283GF05 */
+
 /*----------------------------------------------------------------------*/
 
 #if LCD_BPP == LCD_COLOR8
@@ -292,7 +359,9 @@ static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
 
 	return 0;
 }
-
+#ifdef	CONFIG_CPU_MONAHANS
+static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
+#else
 static void pxafb_setup_gpio (vidinfo_t *vid)
 {
 	u_long lccr0;
@@ -349,6 +418,7 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
 		printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
 	}
 }
+#endif
 
 static void pxafb_enable_controller (vidinfo_t *vid)
 {
@@ -363,7 +433,11 @@ static void pxafb_enable_controller (vidinfo_t *vid)
 	FDADR1 = vid->pxa.fdadr1;
 	LCCR0 |= LCCR0_ENB;
 
+#ifdef	CONFIG_CPU_MONAHANS
+	CKENA |= CKENA_1_LCD;
+#else
 	CKEN |= CKEN16_LCD;
+#endif
 
 	debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
 	debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);