X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Ftegra-common%2Fclock.c;h=268fb912b502d84f3345841f19325160d5a5fc67;hb=375a4496ff250baf6e4b845c1ebf40e4b3c409a3;hp=49a06334cb1a7b8f6614830cac567a9e4bf6dd64;hpb=9a82b10c6657c5744802971036bb564ebc660291;p=u-boot

diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 49a06334cb..268fb912b5 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -321,17 +321,17 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
 	unsigned effective_rate;
 	int mux_bits, divider_bits, source;
 	int divider;
+	int xdiv = 0;
 
 	/* work out the source clock and set it */
 	source = get_periph_clock_source(periph_id, parent, &mux_bits,
 					 &divider_bits);
 
+	divider = find_best_divider(divider_bits, pll_rate[parent],
+				    rate, &xdiv);
 	if (extra_div)
-		divider = find_best_divider(divider_bits, pll_rate[parent],
-						rate, extra_div);
-	else
-		divider = clk_get_divider(divider_bits, pll_rate[parent],
-					  rate);
+		*extra_div = xdiv;
+
 	assert(divider >= 0);
 	if (adjust_periph_pll(periph_id, source, mux_bits, divider))
 		return -1U;
@@ -557,4 +557,7 @@ void clock_init(void)
 	debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
 	debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
 	debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
+
+	/* Do any special system timer/TSC setup */
+	arch_timer_init();
 }