X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fdts%2Fdra7.dtsi;h=02a136a4661aa1ed172e4926a7a8dabad9e271b9;hb=56246d1e87050bf22198e95c4526331a94c8a520;hp=5570e30eb3c8b985f35c46f42786c4687c6cc32e;hpb=194eded14ccb40af18e1a9fb8ab85903ee0803ef;p=u-boot diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index 5570e30eb3..02a136a466 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -18,6 +18,7 @@ compatible = "ti,dra7xx"; interrupt-parent = <&crossbar_mpu>; + chosen { }; aliases { i2c0 = &i2c1; @@ -56,7 +57,7 @@ interrupt-controller; #interrupt-cells = <3>; reg = <0x0 0x48211000 0x0 0x1000>, - <0x0 0x48212000 0x0 0x1000>, + <0x0 0x48212000 0x0 0x2000>, <0x0 0x48214000 0x0 0x2000>, <0x0 0x48216000 0x0 0x2000>; interrupts = ; @@ -80,11 +81,7 @@ compatible = "arm,cortex-a15"; reg = <0>; - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; + operating-points-v2 = <&cpu0_opp_table>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -98,6 +95,24 @@ }; }; + cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_wkup>; + + opp_nom-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1060000 850000 1150000>; + opp-supported-hw = <0xFF 0x01>; + opp-suspend; + }; + + opp_od-1176000000 { + opp-hz = /bits/ 64 <1176000000>; + opp-microvolt = <1160000 885000 1160000>; + opp-supported-hw = <0xFF 0x02>; + }; + }; + /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. @@ -171,6 +186,7 @@ reg = <0x1400 0x0468>; #address-cells = <1>; #size-cells = <0>; + #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <32>; @@ -180,6 +196,7 @@ scm_conf1: scm_conf@1c04 { compatible = "syscon"; reg = <0x1c04 0x0020>; + #syscon-cells = <2>; }; scm_conf_pcie: scm_conf@1c24 { @@ -271,7 +288,11 @@ #address-cells = <1>; ranges = <0x51000000 0x51000000 0x3000 0x0 0x20000000 0x10000000>; - pcie1: pcie@51000000 { + /** + * To enable PCI endpoint mode, disable the pcie1_rc + * node and enable pcie1_ep mode. + */ + pcie1_rc: pcie@51000000 { compatible = "ti,dra7-pcie"; reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; reg-names = "rc_dbics", "ti_conf", "config"; @@ -281,6 +302,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x20013000 0x13000 0 0xffed000>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; linux,pci-domain = <0>; @@ -292,12 +314,28 @@ <0 0 0 2 &pcie1_intc 2>, <0 0 0 3 &pcie1_intc 3>, <0 0 0 4 &pcie1_intc 4>; + status = "disabled"; pcie1_intc: interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; + + pcie1_ep: pcie_ep@51000000 { + compatible = "ti,dra7-pcie-ep"; + reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; + reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; + interrupts = <0 232 0x4>; + num-lanes = <1>; + num-ib-windows = <4>; + num-ob-windows = <16>; + ti,hwmods = "pcie1"; + phys = <&pcie1_phy>; + phy-names = "pcie-phy0"; + ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; + status = "disabled"; + }; }; axi@1 { @@ -317,6 +355,7 @@ device_type = "pci"; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x30013000 0x13000 0 0xffed000>; + bus-range = <0x00 0xff>; #interrupt-cells = <1>; num-lanes = <1>; linux,pci-domain = <1>; @@ -400,6 +439,14 @@ reg = <0x40d00000 0x100>; }; + dra7_iodelay_core: padconf@4844a000 { + compatible = "ti,dra7-iodelay"; + reg = <0x4844a000 0x0d1c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + }; + sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; @@ -542,7 +589,6 @@ uart1: serial@4806a000 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x4806a000 0x100>; - reg-shift = <2>; interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; clock-frequency = <48000000>; @@ -554,7 +600,6 @@ uart2: serial@4806c000 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x4806c000 0x100>; - reg-shift = <2>; interrupts = ; ti,hwmods = "uart2"; clock-frequency = <48000000>; @@ -566,7 +611,6 @@ uart3: serial@48020000 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x48020000 0x100>; - reg-shift = <2>; interrupts = ; ti,hwmods = "uart3"; clock-frequency = <48000000>; @@ -578,7 +622,6 @@ uart4: serial@4806e000 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x4806e000 0x100>; - reg-shift = <2>; interrupts = ; ti,hwmods = "uart4"; clock-frequency = <48000000>; @@ -590,7 +633,6 @@ uart5: serial@48066000 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x48066000 0x100>; - reg-shift = <2>; interrupts = ; ti,hwmods = "uart5"; clock-frequency = <48000000>; @@ -602,7 +644,6 @@ uart6: serial@48068000 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x48068000 0x100>; - reg-shift = <2>; interrupts = ; ti,hwmods = "uart6"; clock-frequency = <48000000>; @@ -614,7 +655,6 @@ uart7: serial@48420000 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x48420000 0x100>; - reg-shift = <2>; interrupts = ; ti,hwmods = "uart7"; clock-frequency = <48000000>; @@ -624,7 +664,6 @@ uart8: serial@48422000 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x48422000 0x100>; - reg-shift = <2>; interrupts = ; ti,hwmods = "uart8"; clock-frequency = <48000000>; @@ -634,7 +673,6 @@ uart9: serial@48424000 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x48424000 0x100>; - reg-shift = <2>; interrupts = ; ti,hwmods = "uart9"; clock-frequency = <48000000>; @@ -644,7 +682,6 @@ uart10: serial@4ae2b000 { compatible = "ti,dra742-uart", "ti,omap4-uart"; reg = <0x4ae2b000 0x100>; - reg-shift = <2>; interrupts = ; ti,hwmods = "uart10"; clock-frequency = <48000000>; @@ -1029,6 +1066,7 @@ dma-names = "tx", "rx"; status = "disabled"; pbias-supply = <&pbias_mmc_reg>; + max-frequency = <192000000>; }; mmc2: mmc@480b4000 { @@ -1040,6 +1078,7 @@ dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; dma-names = "tx", "rx"; status = "disabled"; + max-frequency = <192000000>; }; mmc3: mmc@480ad000 { @@ -1051,6 +1090,8 @@ dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; dma-names = "tx", "rx"; status = "disabled"; + /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ + max-frequency = <64000000>; }; mmc4: mmc@480d1000 { @@ -1062,6 +1103,7 @@ dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; dma-names = "tx", "rx"; status = "disabled"; + max-frequency = <192000000>; }; mmu0_dsp1: mmu@40d01000 { @@ -1386,6 +1428,7 @@ phy-names = "sata-phy"; clocks = <&sata_ref_clk>; ti,hwmods = "sata"; + ports-implemented = <0x1>; }; rtc: rtc@48838000 { @@ -1716,13 +1759,11 @@ cpdma_channels = <8>; ale_entries = <1024>; bd_ram_size = <0x2000>; - no_bd_ram = <0>; mac_control = <0x20>; slaves = <2>; active_slave = <0>; cpts_clock_mult = <0x784CFE14>; cpts_clock_shift = <29>; - syscon = <&scm_conf>; reg = <0x48484000 0x1000 0x48485200 0x2E00>; #address-cells = <1>; @@ -1748,6 +1789,7 @@ , ; ranges; + syscon = <&scm_conf>; status = "disabled"; davinci_mdio: mdio@48485000 { @@ -1990,6 +2032,27 @@ &cpu_thermal { polling-delay = <500>; /* milliseconds */ + coefficients = <0 2000>; +}; + +&gpu_thermal { + coefficients = <0 2000>; +}; + +&core_thermal { + coefficients = <0 2000>; +}; + +&dspeve_thermal { + coefficients = <0 2000>; +}; + +&iva_thermal { + coefficients = <0 2000>; +}; + +&cpu_crit { + temperature = <120000>; /* milli Celsius */ }; /include/ "dra7xx-clocks.dtsi"