X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fdts%2Fexynos5250-snow.dts;h=bda549998861c65b6cfd66c9c29a4fc68996c3fb;hb=fbb0c7bd92255bfcb13826a8ac81be6e2f94ba48;hp=653efb4175b29d91252050ad9a18373c5885f22b;hpb=a0942a6d3e08490be2871396c977fb5520ecdf33;p=u-boot

diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
index 653efb4175..bda5499988 100644
--- a/arch/arm/dts/exynos5250-snow.dts
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -43,18 +43,55 @@
 		i2s = "/sound@3830000";
 	};
 
-	i2c4: i2c@12CA0000 {
-		cros_ec_old: cros-ec@1e {
-			reg = <0x1e>;
-			compatible = "google,cros-ec-i2c";
-			i2c-max-frequency = <100000>;
-			u-boot,i2c-offset-len = <0>;
-			ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
+        memory {
+		reg = <0x40000000 0x80000000>;
+	};
+
+	chosen {
+		bootargs = "console=tty1";
+		stdout-path = "serial3:115200n8";
+	};
+
+	iram {
+		reg = <0x02020000 0x60000>;
+	};
+
+	config {
+		samsung,bl1-offset = <0x1400>;
+		samsung,bl2-offset = <0x3400>;
+		u-boot-memory = "/memory";
+		u-boot-offset = <0x3e00000 0x100000>;
+	};
+
+	flash {
+		reg = <0 0x100000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		pre-boot {
+			label = "bl1 pre-boot";
+			reg = <0 0x2000>;
+			read-only;
+			filename = "e5250.nbl1.bin";
+			type = "blob exynos-bl1";
+			required;
 		};
 
-		power-regulator@48 {
-			compatible = "ti,tps65090";
-			reg = <0x48>;
+		spl {
+			label = "bl2 spl";
+			reg = <0x2000 0x4000>;
+			read-only;
+			filename = "bl2.bin";
+			type = "blob exynos-bl2 boot,dtb";
+			payload = "/flash/ro-boot";
+			required;
+		};
+
+		ro-boot {
+			label = "u-boot";
+			reg = <0x6000 0x9a000>;
+			read-only;
+			type = "blob boot,dtb";
+			required;
 		};
 	};
 
@@ -153,6 +190,31 @@
 		};
 	};
 
+	i2c@12CD0000 {
+		ptn3460: lvds-bridge@20 {
+			compatible = "nxp,ptn3460";
+			reg = <0x20>;
+			sleep-gpios = <&gpy2 5 GPIO_ACTIVE_LOW>;
+			reset-gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
+			hotplug-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+			edid-emulation = <5>;
+		};
+
+		soundcodec@22 {
+			reg = <0x22>;
+			compatible = "maxim,max98095-codec";
+		};
+	};
+
+	i2c@12C90000 {
+		clock-frequency = <100000>;
+		tpm@20 {
+			reg = <0x20>;
+			u-boot,i2c-offset-len = <0>;
+			compatible = "infineon,slb9635tt";
+		};
+	};
+
 	spi@12d30000 {
 		spi-max-frequency = <50000000>;
 		firmware_storage_spi: flash@0 {
@@ -185,26 +247,6 @@
 		status = "disabled";
 	};
 
-	i2c@12CD0000 {
-		soundcodec@22 {
-			reg = <0x22>;
-			compatible = "maxim,max98095-codec";
-		};
-
-		ptn3460-bridge@20 {
-			compatible = "nxp,ptn3460";
-			reg = <0x20>;
-			/*
-			 * TODO(sjg@chromium.org): Use GPIOs here
-			 * powerdown-gpio = <&gpy2 5 0>;
-			 * reset-gpio = <&gpx1 5 0>;
-			 * edid-emulation = <5>;
-			 * pinctrl-names = "default";
-			 * pinctrl-0 = <&ptn3460_gpios>;
-			 */
-		};
-	};
-
 	i2c@12C60000 {
 		max77686@09 {
 			reg = <0x9>;