X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fdts%2Fhi6220.dtsi;h=a610ccb63463ccbbb2bf58ada4edf8f1796c71c2;hb=7e4902d47933eeeadb2eb5505683ffafa96691b7;hp=ad1f1ebcb05c9c5e5fa207774a998105628222e8;hpb=9122109ad75ebf7ac2380ddd5d49b981899c9a67;p=u-boot

diff --git a/arch/arm/dts/hi6220.dtsi b/arch/arm/dts/hi6220.dtsi
index ad1f1ebcb0..a610ccb634 100644
--- a/arch/arm/dts/hi6220.dtsi
+++ b/arch/arm/dts/hi6220.dtsi
@@ -166,6 +166,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf8015000 0x0 0x1000>;
 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&ao_ctrl HI6220_UART0_PCLK>,
 				 <&ao_ctrl HI6220_UART0_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -175,6 +176,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7111000 0x0 0x1000>;
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART1_PCLK>,
 				 <&sys_ctrl HI6220_UART1_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -185,6 +187,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7112000 0x0 0x1000>;
 			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART2_PCLK>,
 				 <&sys_ctrl HI6220_UART2_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -195,6 +198,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7113000 0x0 0x1000>;
 			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART3_PCLK>,
 				 <&sys_ctrl HI6220_UART3_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -204,6 +208,7 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7114000 0x0 0x1000>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART4_PCLK>,
 				 <&sys_ctrl HI6220_UART4_PCLK>;
 			clock-names = "uartclk", "apb_pclk";