X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fdts%2Fsocfpga_arria5_socdk.dts;h=449ba9cbb964a90ce60f0613198ac6a09032dbfb;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=5933a406cb05191380a8519be8a1fa8e51b4d465;hpb=f1993ca066100fcaba7d49fecae0ef604e5807e2;p=u-boot

diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
index 5933a406cb..449ba9cbb9 100644
--- a/arch/arm/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include "socfpga_arria5.dtsi"
@@ -21,7 +20,7 @@
 	};
 
 	aliases {
-		/* this allow the ethaddr uboot environmnet variable contents
+		/* this allow the ethaddr uboot environment variable contents
 		 * to be added to the gmac1 device tree blob.
 		 */
 		ethernet0 = &gmac1;
@@ -82,20 +81,21 @@
 
 &qspi {
 	status = "okay";
+	u-boot,dm-pre-reloc;
 
 	flash0: n25q00@0 {
+		u-boot,dm-pre-reloc;
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "n25q00";
+		compatible = "n25q00", "spi-flash";
 		reg = <0>;      /* chip select */
 		spi-max-frequency = <50000000>;
 		m25p,fast-read;
 		page-size = <256>;
 		block-size = <16>; /* 2^16, 64KB */
-		read-delay = <4>;  /* delay value in read data capture register */
-		tshsl-ns = <50>;
-		tsd2d-ns = <50>;
-		tchsh-ns = <4>;
-		tslch-ns = <4>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
 	};
 };