X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fdts%2Ftegra20-trimslice.dts;h=db13ff965178dcedb0df08312493432ffc3cfdc4;hb=9f03247edc7761b608db31104821b4518a70e691;hp=1637cbd58e32ec4e6f7a4eaf526b348d2fc64f45;hpb=7dd8738f08144b01d91185f250af9ce2648cb25f;p=u-boot

diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts
index 1637cbd58e..db13ff9651 100644
--- a/arch/arm/dts/tegra20-trimslice.dts
+++ b/arch/arm/dts/tegra20-trimslice.dts
@@ -26,27 +26,11 @@
 		clock-frequency = <216000000>;
 	};
 
-	i2c@7000c000 {
-		status = "disabled";
-	};
-
 	spi@7000c380 {
 		status = "okay";
 		spi-max-frequency = <25000000>;
 	};
 
-	i2c@7000c400 {
-		status = "disabled";
-	};
-
-	i2c@7000c500 {
-		status = "disabled";
-	};
-
-	i2c@7000d000 {
-		status = "disabled";
-	};
-
 	pcie-controller@80003000 {
 		status = "okay";
 
@@ -62,11 +46,8 @@
 	};
 
 	usb@c5000000 {
-		nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */
-	};
-
-	usb@c5004000 {
-		status = "disabled";
+		status = "okay";
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 	};
 
 	sdhci@c8000000 {
@@ -76,11 +57,24 @@
 
 	sdhci@c8000600 {
 		status = "okay";
-		cd-gpios = <&gpio 121 1>; /* gpio PP1 */
-		wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+		cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
 		bus-width = <4>;
 	};
 
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clk32k_in: clock@0 {
+			compatible = "fixed-clock";
+			reg=<0>;
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -111,7 +105,7 @@
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			enable-active-high;
-			gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
+			gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 			regulator-always-on;
 			regulator-boot-on;
 		};