X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fdts%2Fzynqmp-ep108-clk.dtsi;h=12d9fe14988831b0e357fd0ef4af2a1b4acace97;hb=c0ce4ceaba03fa6ddf738628344025c44fc78dd4;hp=48bb426dafaf2bd4d6eb1c529390e5490d347cc1;hpb=541c9be880d601cb0230dc7452c398167ed1eaac;p=u-boot

diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi
index 48bb426daf..12d9fe1498 100644
--- a/arch/arm/dts/zynqmp-ep108-clk.dtsi
+++ b/arch/arm/dts/zynqmp-ep108-clk.dtsi
@@ -8,11 +8,12 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-&amba {
+/ {
 	misc_clk: misc_clk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <25000000>;
+		u-boot,dm-pre-reloc;
 	};
 
 	i2c_clk: i2c_clk {
@@ -34,6 +35,18 @@
 		clock-accuracy = <100>;
 	};
 
+	clk100: clk100 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	clk600: clk600 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <600000000>;
+	};
+
 	dp_aud_clk: clock1 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -46,6 +59,42 @@
 	clocks = <&misc_clk &misc_clk>;
 };
 
+&can1 {
+	clocks = <&misc_clk &misc_clk>;
+};
+
+&fpd_dma_chan1 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan2 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan3 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan4 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan5 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan6 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan7 {
+	clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan8 {
+	clocks = <&clk600>, <&clk100>;
+};
+
 &gem0 {
 	clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
 };