X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fimx-common%2Ftimer.c;h=ee6eff2b28cada0fca04044a90873246d879454f;hb=2c45f8040ea1152d2ff0960f96905ca42ac089cd;hp=a01590ced2261c28d3ad9d02505eb7d6a9f58f70;hpb=232d77e7238e41779f952094b302c47caea4d159;p=u-boot

diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index a01590ced2..ee6eff2b28 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -44,7 +44,8 @@ static inline int gpt_has_clk_source_osc(void)
 {
 #if defined(CONFIG_MX6)
 	if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
-	    is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul())
+	    is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
+	    is_mx6ull() || is_mx6sll())
 		return 1;
 
 	return 0;
@@ -83,8 +84,12 @@ int timer_init(void)
 	if (gpt_has_clk_source_osc()) {
 		i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
 
-		/* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
-		if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) {
+		/*
+		 * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC
+		 * Enable bit and prescaler
+		 */
+		if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
+		    is_mx6sll()) {
 			i |= GPTCR_24MEN;
 
 			/* Produce 3Mhz clock */
@@ -119,3 +124,19 @@ ulong get_tbclk(void)
 {
 	return gpt_get_clk();
 }
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long _usec)
+{
+	unsigned long long usec = _usec;
+
+	usec *= get_tbclk();
+	usec += 999999;
+	do_div(usec, 1000000);
+
+	return usec;
+}