X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-davinci%2Fhardware.h;h=98fe56e68653023b4c30695ee4859fee36ac792a;hb=c9aab0f9dd23fddcebf5984dc19e62b514e759a7;hp=dd89e84413bb4e890c556d30dd37148610038ffb;hpb=c786f54b9ace5d7b20a0404a7deb1bae683cd4e8;p=u-boot diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index dd89e84413..98fe56e686 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -9,32 +9,13 @@ * * Copyright (C) 2006 Texas Instruments. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __ASM_ARCH_HARDWARE_H #define __ASM_ARCH_HARDWARE_H #include -#include +#include #define REG(addr) (*(volatile unsigned int *)(addr)) #define REG_P(addr) ((volatile unsigned int *)(addr)) @@ -306,6 +287,7 @@ typedef volatile unsigned int * dv_reg_p; void lpsc_on(unsigned int id); void lpsc_syncreset(unsigned int id); +void lpsc_disable(unsigned int id); void dsp_on(void); void davinci_enable_uart0(void); @@ -345,6 +327,8 @@ void davinci_errata_workarounds(void); #define PSC_PSC0_MODULE_ID_CNT 16 #define PSC_PSC1_MODULE_ID_CNT 32 +#define UART0_PWREMU_MGMT (0x01c42030) + struct davinci_psc_regs { dv_reg revid; dv_reg rsvd0[71]; @@ -441,21 +425,51 @@ struct davinci_pllc_regs { #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE) #define DAVINCI_PLLC_DIV_MASK 0x1f -#define ASYNC3 get_async3_src() -#define PLL1_SYSCLK2 ((1 << 16) | 0x2) -#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3) -/* Clock IDs */ +/* + * A clock ID is a 32-bit number where bit 16 represents the PLL controller + * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor, + * counting from 1. Clock IDs may be passed to clk_get(). + */ + +/* flags to select PLL controller */ +#define DAVINCI_PLLC0_FLAG (0) +#define DAVINCI_PLLC1_FLAG (1 << 16) + enum davinci_clk_ids { - DAVINCI_SPI0_CLKID = 2, - DAVINCI_UART2_CLKID = 2, - DAVINCI_MMC_CLKID = 2, - DAVINCI_MDIO_CLKID = 4, - DAVINCI_ARM_CLKID = 6, - DAVINCI_PLLM_CLKID = 0xff, - DAVINCI_PLLC_CLKID = 0x100, - DAVINCI_AUXCLK_CLKID = 0x101 + /* + * Clock IDs for PLL outputs. Each may be switched on/off + * independently, and each may map to one or more peripherals. + */ + DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2, + DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4, + DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6, + DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1, + DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2, + + /* map peripherals to clock IDs */ + DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6, + DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1, + DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4, + DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2, + DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2, + DAVINCI_MMCSD_CLKID = DAVINCI_PLL0_SYSCLK2, + + /* special clock ID - output of PLL multiplier */ + DAVINCI_PLLM_CLKID = 0x0FF, + + /* special clock ID - output of PLL post divisor */ + DAVINCI_PLLC_CLKID = 0x100, + + /* special clock ID - PLL bypass */ + DAVINCI_AUXCLK_CLKID = 0x101, }; +#define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \ + : get_async3_src()) + +#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \ + : get_async3_src()) + int clk_get(enum davinci_clk_ids id); /* Boot config */ @@ -464,8 +478,9 @@ struct davinci_syscfg_regs { dv_reg rsvd[13]; dv_reg kick0; dv_reg kick1; - dv_reg rsvd1[53]; + dv_reg rsvd1[52]; dv_reg mstpri[3]; + dv_reg rsvd2; dv_reg pinmux[20]; dv_reg suspsrc; dv_reg chipsig; @@ -505,6 +520,7 @@ struct davinci_syscfg1_regs { ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE) #define DDR_SLEW_CMOSEN_BIT 4 +#define DDR_SLEW_DDR_PDENA_BIT 5 #define VTP_POWERDWN (1 << 6) #define VTP_LOCK (1 << 7) @@ -570,10 +586,10 @@ static inline int cpu_is_da850(void) return ((part_no == 0xb7d1) ? 1 : 0); } -static inline int get_async3_src(void) +static inline enum davinci_clk_ids get_async3_src(void) { return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ? - PLL1_SYSCLK2 : 2; + DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2; } #endif /* CONFIG_SOC_DA8XX */ @@ -587,44 +603,15 @@ static inline int get_async3_src(void) #include #include #include -#endif -struct davinci_rtc { - dv_reg second; - dv_reg minutes; - dv_reg hours; - dv_reg day; - dv_reg month; /* 0x10 */ - dv_reg year; - dv_reg dotw; - dv_reg resv1; - dv_reg alarmsecond; /* 0x20 */ - dv_reg alarmminute; - dv_reg alarmhour; - dv_reg alarmday; - dv_reg alarmmonth; /* 0x30 */ - dv_reg alarmyear; - dv_reg resv2[2]; - dv_reg ctrl; /* 0x40 */ - dv_reg status; - dv_reg irq; - dv_reg complsb; - dv_reg compmsb; /* 0x50 */ - dv_reg osc; - dv_reg resv3[2]; - dv_reg scratch0; /* 0x60 */ - dv_reg scratch1; - dv_reg scratch2; - dv_reg kick0r; - dv_reg kick1r; /* 0x70 */ -}; +#define TMPBUF 0x00017ff8 +#define TMPSTATUS 0x00017ff0 +#define DV_TMPBUF_VAL 0x591b3ed7 +#define FLAG_PORRST 0x00000001 +#define FLAG_WDTRST 0x00000002 +#define FLAG_FLGON 0x00000004 +#define FLAG_FLGOFF 0x00000010 -#define RTC_STATE_BUSY 0x01 -#define RTC_STATE_RUN 0x02 - -#define RTC_KICK0R_WE 0x130be783 -#define RTC_KICK1R_WE 0xe0f1a495 - -#define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE) +#endif #endif /* __ASM_ARCH_HARDWARE_H */