X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-exynos%2Fcpu.h;h=4b67191c07e214d25de6bcbe42ab31ff1ae0ed4e;hb=5fb5b1554172167a4295880ac71439aa3e88f2b8;hp=89f2c2e3e904380b508b44e25d6fa7744a008b12;hpb=e9d44b35beb45869863f3ca6929089d9df4df3e5;p=u-boot

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 89f2c2e3e9..4b67191c07 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -2,21 +2,7 @@
  * (C) Copyright 2010 Samsung Electronics
  * Minkyu Kang <mk7.kang@samsung.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef _EXYNOS4_CPU_H
@@ -24,55 +10,116 @@
 
 #define DEVICE_NOT_AVAILABLE		0
 
+#define EXYNOS_CPU_NAME			"Exynos"
 #define EXYNOS4_ADDR_BASE		0x10000000
 
-/* EXYNOS4 */
+/* EXYNOS4 Common*/
+#define EXYNOS4_I2C_SPACING		0x10000
+
 #define EXYNOS4_GPIO_PART3_BASE		0x03860000
 #define EXYNOS4_PRO_ID			0x10000000
+#define EXYNOS4_SYSREG_BASE		0x10010000
 #define EXYNOS4_POWER_BASE		0x10020000
 #define EXYNOS4_SWRESET			0x10020400
 #define EXYNOS4_CLOCK_BASE		0x10030000
 #define EXYNOS4_SYSTIMER_BASE		0x10050000
 #define EXYNOS4_WATCHDOG_BASE		0x10060000
+#define EXYNOS4_TZPC_BASE		0x10110000
 #define EXYNOS4_MIU_BASE		0x10600000
-#define EXYNOS4_DMC0_BASE		0x10400000
-#define EXYNOS4_DMC1_BASE		0x10410000
+#define EXYNOS4_DMC_CTRL_BASE		0x10400000
 #define EXYNOS4_GPIO_PART2_BASE		0x11000000
 #define EXYNOS4_GPIO_PART1_BASE		0x11400000
 #define EXYNOS4_FIMD_BASE		0x11C00000
+#define EXYNOS4_MIPI_DSIM_BASE		0x11C80000
 #define EXYNOS4_USBOTG_BASE		0x12480000
 #define EXYNOS4_MMC_BASE		0x12510000
 #define EXYNOS4_SROMC_BASE		0x12570000
+#define EXYNOS4_USB_HOST_EHCI_BASE	0x12580000
 #define EXYNOS4_USBPHY_BASE		0x125B0000
 #define EXYNOS4_UART_BASE		0x13800000
+#define EXYNOS4_I2C_BASE		0x13860000
 #define EXYNOS4_ADC_BASE		0x13910000
+#define EXYNOS4_SPI_BASE		0x13920000
 #define EXYNOS4_PWMTIMER_BASE		0x139D0000
 #define EXYNOS4_MODEM_BASE		0x13A00000
 #define EXYNOS4_USBPHY_CONTROL		0x10020704
+#define EXYNOS4_I2S_BASE		0xE2100000
 
 #define EXYNOS4_GPIO_PART4_BASE		DEVICE_NOT_AVAILABLE
-
-/* EXYNOS5 */
+#define EXYNOS4_DP_BASE			DEVICE_NOT_AVAILABLE
+#define EXYNOS4_SPI_ISP_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4_ACE_SFR_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4_DMC_PHY_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4_AUDIOSS_BASE		DEVICE_NOT_AVAILABLE
+
+/* EXYNOS4X12 */
+#define EXYNOS4X12_GPIO_PART3_BASE	0x03860000
+#define EXYNOS4X12_PRO_ID		0x10000000
+#define EXYNOS4X12_SYSREG_BASE		0x10010000
+#define EXYNOS4X12_POWER_BASE		0x10020000
+#define EXYNOS4X12_SWRESET		0x10020400
+#define EXYNOS4X12_USBPHY_CONTROL	0x10020704
+#define EXYNOS4X12_CLOCK_BASE		0x10030000
+#define EXYNOS4X12_SYSTIMER_BASE	0x10050000
+#define EXYNOS4X12_WATCHDOG_BASE	0x10060000
+#define EXYNOS4X12_TZPC_BASE		0x10110000
+#define EXYNOS4X12_DMC_CTRL_BASE	0x10600000
+#define EXYNOS4X12_GPIO_PART4_BASE	0x106E0000
+#define EXYNOS4X12_GPIO_PART2_BASE	0x11000000
+#define EXYNOS4X12_GPIO_PART1_BASE	0x11400000
+#define EXYNOS4X12_FIMD_BASE		0x11C00000
+#define EXYNOS4X12_MIPI_DSIM_BASE	0x11C80000
+#define EXYNOS4X12_USBOTG_BASE		0x12480000
+#define EXYNOS4X12_MMC_BASE		0x12510000
+#define EXYNOS4X12_SROMC_BASE		0x12570000
+#define EXYNOS4X12_USB_HOST_EHCI_BASE	0x12580000
+#define EXYNOS4X12_USBPHY_BASE		0x125B0000
+#define EXYNOS4X12_UART_BASE		0x13800000
+#define EXYNOS4X12_I2C_BASE		0x13860000
+#define EXYNOS4X12_PWMTIMER_BASE	0x139D0000
+
+#define EXYNOS4X12_ADC_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DP_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_MODEM_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_I2S_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_ISP_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_ACE_SFR_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DMC_PHY_BASE		DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_AUDIOSS_BASE		DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5 Common*/
+#define EXYNOS5_I2C_SPACING		0x10000
+
+#define EXYNOS5_AUDIOSS_BASE		0x03810000
 #define EXYNOS5_GPIO_PART4_BASE		0x03860000
 #define EXYNOS5_PRO_ID			0x10000000
 #define EXYNOS5_CLOCK_BASE		0x10010000
 #define EXYNOS5_POWER_BASE		0x10040000
 #define EXYNOS5_SWRESET			0x10040400
 #define EXYNOS5_SYSREG_BASE		0x10050000
+#define EXYNOS5_TZPC_BASE		0x10100000
 #define EXYNOS5_WATCHDOG_BASE		0x101D0000
-#define EXYNOS5_DMC_PHY0_BASE		0x10C00000
-#define EXYNOS5_DMC_PHY1_BASE		0x10C10000
+#define EXYNOS5_ACE_SFR_BASE            0x10830000
+#define EXYNOS5_DMC_PHY_BASE		0x10C00000
 #define EXYNOS5_GPIO_PART3_BASE		0x10D10000
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
+#define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
+#define EXYNOS5_USB_HOST_EHCI_BASE	0x12110000
+#define EXYNOS5_USBPHY_BASE		0x12130000
+#define EXYNOS5_USBOTG_BASE		0x12140000
 #define EXYNOS5_MMC_BASE		0x12200000
 #define EXYNOS5_SROMC_BASE		0x12250000
-#define EXYNOS5_USBOTG_BASE		0x12480000
-#define EXYNOS5_USBPHY_BASE		0x12480000
 #define EXYNOS5_UART_BASE		0x12C00000
+#define EXYNOS5_I2C_BASE		0x12C60000
+#define EXYNOS5_SPI_BASE		0x12D20000
+#define EXYNOS5_I2S_BASE		0x12D60000
 #define EXYNOS5_PWMTIMER_BASE		0x12DD0000
+#define EXYNOS5_SPI_ISP_BASE		0x131A0000
 #define EXYNOS5_GPIO_PART2_BASE		0x13400000
 #define EXYNOS5_FIMD_BASE		0x14400000
+#define EXYNOS5_DP_BASE			0x145B0000
 
 #define EXYNOS5_ADC_BASE		DEVICE_NOT_AVAILABLE
 #define EXYNOS5_MODEM_BASE		DEVICE_NOT_AVAILABLE
@@ -90,44 +137,77 @@ static inline int s5p_get_cpu_rev(void)
 
 static inline void s5p_set_cpu_id(void)
 {
-	s5p_cpu_id = readl(EXYNOS4_PRO_ID);
-	s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
-
-	/*
-	 * 0xC200: EXYNOS4210 EVT0
-	 * 0xC210: EXYNOS4210 EVT1
-	 */
-	if (s5p_cpu_id == 0xC200) {
-		s5p_cpu_id |= 0x10;
+	unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
+
+	switch (pro_id) {
+	case 0x200:
+		/* Exynos4210 EVT0 */
+		s5p_cpu_id = 0x4210;
 		s5p_cpu_rev = 0;
-	} else if (s5p_cpu_id == 0xC210) {
-		s5p_cpu_rev = 1;
+		break;
+	case 0x210:
+		/* Exynos4210 EVT1 */
+		s5p_cpu_id = 0x4210;
+		break;
+	case 0x412:
+		/* Exynos4412 */
+		s5p_cpu_id = 0x4412;
+		break;
+	case 0x520:
+		/* Exynos5250 */
+		s5p_cpu_id = 0x5250;
+		break;
 	}
 }
 
+static inline char *s5p_get_cpu_name(void)
+{
+	return EXYNOS_CPU_NAME;
+}
+
 #define IS_SAMSUNG_TYPE(type, id)			\
-static inline int cpu_is_##type(void)			\
+static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \
+{							\
+	return (s5p_cpu_id >> 12) == id;		\
+}
+
+IS_SAMSUNG_TYPE(exynos4, 0x4)
+IS_SAMSUNG_TYPE(exynos5, 0x5)
+
+#define IS_EXYNOS_TYPE(type, id)			\
+static inline int __attribute__((no_instrument_function)) \
+	proid_is_##type(void)				\
 {							\
-	return s5p_cpu_id == id ? 1 : 0;		\
+	return s5p_cpu_id == id;			\
 }
 
-IS_SAMSUNG_TYPE(exynos4, 0xc210)
-IS_SAMSUNG_TYPE(exynos5, 0xc520)
+IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos4412, 0x4412)
+IS_EXYNOS_TYPE(exynos5250, 0x5250)
 
 #define SAMSUNG_BASE(device, base)				\
-static inline unsigned int samsung_get_base_##device(void)	\
+static inline unsigned int __attribute__((no_instrument_function)) \
+	samsung_get_base_##device(void) \
 {								\
-	if (cpu_is_exynos4())					\
+	if (cpu_is_exynos4()) {				\
+		if (proid_is_exynos4412())			\
+			return EXYNOS4X12_##base;		\
 		return EXYNOS4_##base;				\
-	else if (cpu_is_exynos5())				\
+	} else if (cpu_is_exynos5()) {				\
 		return EXYNOS5_##base;				\
-	else							\
-		return 0;					\
+	}							\
+	return 0;						\
 }
 
 SAMSUNG_BASE(adc, ADC_BASE)
 SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
+SAMSUNG_BASE(dp, DP_BASE)
+SAMSUNG_BASE(sysreg, SYSREG_BASE)
 SAMSUNG_BASE(fimd, FIMD_BASE)
+SAMSUNG_BASE(i2c, I2C_BASE)
+SAMSUNG_BASE(i2s, I2S_BASE)
+SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
 SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
@@ -140,9 +220,16 @@ SAMSUNG_BASE(swreset, SWRESET)
 SAMSUNG_BASE(timer, PWMTIMER_BASE)
 SAMSUNG_BASE(uart, UART_BASE)
 SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
 SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 SAMSUNG_BASE(power, POWER_BASE)
+SAMSUNG_BASE(spi, SPI_BASE)
+SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
+SAMSUNG_BASE(tzpc, TZPC_BASE)
+SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
+SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
+SAMSUNG_BASE(audio_ass, AUDIOSS_BASE)
 #endif
 
 #endif	/* _EXYNOS4_CPU_H */