X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-exynos%2Fi2s-regs.h;h=4a4a7a00b7a2437d5090867b32ede78498a646bf;hb=748bde608a8dfea5b64e186af4d9c27642fe7813;hp=613b9b7a372fb5505f9837f693be7fc8e5e3809d;hpb=c2120fbfbc4d1f6953228f86be8bdbf38bacfdab;p=u-boot

diff --git a/arch/arm/include/asm/arch-exynos/i2s-regs.h b/arch/arm/include/asm/arch-exynos/i2s-regs.h
index 613b9b7a37..4a4a7a00b7 100644
--- a/arch/arm/include/asm/arch-exynos/i2s-regs.h
+++ b/arch/arm/include/asm/arch-exynos/i2s-regs.h
@@ -8,10 +8,12 @@
 #ifndef __I2S_REGS_H__
 #define __I2S_REGS_H__
 
+#define CON_RESET		(1 << 31)
 #define CON_TXFIFO_FULL		(1 << 8)
 #define CON_TXCH_PAUSE		(1 << 4)
 #define CON_ACTIVE		(1 << 0)
 
+#define MOD_OP_CLK		(3 << 30)
 #define MOD_BLCP_SHIFT		24
 #define MOD_BLCP_16BIT		(0 << MOD_BLCP_SHIFT)
 #define MOD_BLCP_8BIT		(1 << MOD_BLCP_SHIFT)
@@ -24,6 +26,7 @@
 #define MOD_BLC_MASK		(3 << 13)
 
 #define MOD_SLAVE		(1 << 11)
+#define MOD_RCLKSRC		(0 << 10)
 #define MOD_MASK		(3 << 8)
 #define MOD_LR_LLOW		(0 << 7)
 #define MOD_LR_RLOW		(1 << 7)
@@ -47,4 +50,7 @@
 #define FIC_TXFLUSH		(1 << 15)
 #define FIC_RXFLUSH		(1 << 7)
 
+#define PSREN			(1 << 15)
+#define PSVAL			(3 << 8)
+
 #endif /* __I2S_REGS_H__ */