X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-lpc32xx%2Fconfig.h;h=3b7f6bdb720fe867be9f83d8388e3e962a250699;hb=f46c25583a73042edf432b209ee4b93bc3f7e762;hp=8f6426bc1b0184d4c362487ca499268aa7e783f1;hpb=fc9b0b80435cda721fbdbe507c9e4f388b0ea62b;p=u-boot

diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index 8f6426bc1b..3b7f6bdb72 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -1,7 +1,7 @@
 /*
  * Common definitions for LPC32XX board configurations
  *
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -9,46 +9,64 @@
 #ifndef _LPC32XX_CONFIG_H
 #define _LPC32XX_CONFIG_H
 
+
 /* Basic CPU architecture */
 #define CONFIG_ARCH_CPU_INIT
 
 #define CONFIG_NR_DRAM_BANKS_MAX	2
 
 /* UART configuration */
-#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6)
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_CONS_INDEX		(CONFIG_SYS_LPC32XX_UART - 2)
-#elif	(CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
+#if	(CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
 	(CONFIG_SYS_LPC32XX_UART == 7)
+#if !defined(CONFIG_LPC32XX_HSUART)
 #define CONFIG_LPC32XX_HSUART
+#endif
+#endif
+
+#if !defined(CONFIG_SYS_NS16550_CLK)
+#define CONFIG_SYS_NS16550_CLK		13000000
+#endif
+
+#if !defined(CONFIG_LPC32XX_HSUART)
+#define CONFIG_CONS_INDEX		(CONFIG_SYS_LPC32XX_UART - 2)
 #else
-#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7"
+#define CONFIG_CONS_INDEX		CONFIG_SYS_LPC32XX_UART
 #endif
 
-#if defined(CONFIG_SYS_NS16550_SERIAL)
-#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+		{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
 
-#define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+/* Ethernet */
+#define LPC32XX_ETH_BASE ETHERNET_BASE
 
-#define CONFIG_SYS_NS16550_COM1		UART3_BASE
-#define CONFIG_SYS_NS16550_COM2		UART4_BASE
-#define CONFIG_SYS_NS16550_COM3		UART5_BASE
-#define CONFIG_SYS_NS16550_COM4		UART6_BASE
-#endif
+/* NAND */
+#if defined(CONFIG_NAND_LPC32XX_SLC)
+#define NAND_LARGE_BLOCK_PAGE_SIZE	0x800
+#define NAND_SMALL_BLOCK_PAGE_SIZE	0x200
 
-#if defined(CONFIG_LPC32XX_HSUART)
-#if	CONFIG_SYS_LPC32XX_UART == 1
-#define HS_UART_BASE			HS_UART1_BASE
-#elif	CONFIG_SYS_LPC32XX_UART == 2
-#define HS_UART_BASE			HS_UART2_BASE
-#else	/* CONFIG_SYS_LPC32XX_UART == 7 */
-#define HS_UART_BASE			HS_UART7_BASE
+#if !defined(CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	NAND_LARGE_BLOCK_PAGE_SIZE
 #endif
+
+#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+					  48, 49, 50, 51, 52, 53, 54, 55, \
+					  56, 57, 58, 59, 60, 61, 62, 63, }
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
+#define CONFIG_SYS_NAND_OOBSIZE		16
+#define CONFIG_SYS_NAND_ECCPOS		{ 10, 11, 12, 13, 14, 15, }
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#else
+#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
 #endif
 
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-		{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
+#define CONFIG_SYS_NAND_ECCSIZE		0x100
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+						CONFIG_SYS_NAND_PAGE_SIZE)
+#endif	/* CONFIG_NAND_LPC32XX_SLC */
 
 /* NOR Flash */
 #if defined(CONFIG_SYS_FLASH_CFI)
@@ -56,4 +74,13 @@
 #define CONFIG_SYS_FLASH_PROTECTION
 #endif
 
+/* USB OHCI */
+#if defined(CONFIG_USB_OHCI_LPC32XX)
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		USB_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"lpc32xx-ohci"
+#endif
+
 #endif /* _LPC32XX_CONFIG_H */