X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-mx6%2Fiomux.h;h=907cb408ff25d3d4e40d15df86b96408c3de90ec;hb=6e2941d787819ae1221d7f8295fa67d2ba94a913;hp=6a4a6321995b8832bf02544eaa71b0dbb9722901;hpb=bad40e089f2c1a0e42fa659611f85028c872cb96;p=u-boot diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index 6a4a632199..907cb408ff 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -18,6 +18,14 @@ #define IOMUXC_GPR1_REF_SSP_EN (1 << 16) #define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) +#define IOMUXC_GPR1_PCIE_SW_RST (1 << 29) + +/* + * IOMUXC_GPR5 bit fields + */ +#define IOMUXC_GPR5_PCIE_BTNRST (1 << 19) +#define IOMUXC_GPR5_PCIE_PERST (1 << 18) + /* * IOMUXC_GPR8 bit fields */ @@ -35,12 +43,15 @@ /* * IOMUXC_GPR12 bit fields */ +#define IOMUXC_GPR12_RX_EQ_2 (0x2 << 0) +#define IOMUXC_GPR12_RX_EQ_MASK (0x7 << 0) #define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) #define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) #define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) #define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) #define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12) #define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) +#define IOMUXC_GPR12_TEST_POWERDOWN (1 << 30) /* * IOMUXC_GPR13 bit fields @@ -65,6 +76,16 @@ #define IOMUX_GPR1_FEC_MASK (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \ | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK) +#define IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK (0x1 << 17) +#define IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK (0x1 << 13) +#define IOMUX_GPR1_FEC1_MASK (IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \ + | IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK) + +#define IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK (0x1 << 18) +#define IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK (0x1 << 14) +#define IOMUX_GPR1_FEC2_MASK (IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK \ + | IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK) + #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB (0<<24) #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB (1<<24) #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB (2<<24)