X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-s5pc1xx%2Fgpio.h;h=00e498d834b3dea2164cbdfc0dcdec40999fa16f;hb=2c601c7208713ba9b2158c57adcf515f4bdbc212;hp=2df33a607c0ac43a09a6d070fdc812461b68e640;hpb=cf64fda38e3d71e9077e11c673bd9be449c680da;p=u-boot

diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
index 2df33a607c..00e498d834 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
@@ -126,14 +126,32 @@ struct s5pc110_gpio {
 };
 
 /* functions */
-void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
-void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
-void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
-void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
-unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
-void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
-void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
-void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
+void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
+void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
+void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
+void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
+unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
+void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
+void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
+void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
+
+/* GPIO pins per bank  */
+#define GPIO_PER_BANK 8
+
+static inline unsigned int s5p_gpio_base(int nr)
+{
+	return S5PC110_GPIO_BASE;
+}
+
+static inline unsigned int s5p_gpio_part_max(int nr)
+{
+	return 0;
+}
+
+#define s5pc110_gpio_get_nr(bank, pin)	  \
+	((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
+	    - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
+	  * GPIO_PER_BANK) + pin)
 #endif
 
 /* Pin configurations */
@@ -149,8 +167,8 @@ void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
 
 /* Drive Strength level */
 #define GPIO_DRV_1X	0x0
-#define GPIO_DRV_2X	0x1
-#define GPIO_DRV_3X	0x2
+#define GPIO_DRV_3X	0x1
+#define GPIO_DRV_2X	0x2
 #define GPIO_DRV_4X	0x3
 #define GPIO_DRV_FAST	0x0
 #define GPIO_DRV_SLOW	0x1