X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-vf610%2Fimx-regs.h;h=975832343316947ec13aca511cc39a58e7e250d0;hb=edb697cfcc2dda02c5b2a34b3157b8fa8fc01264;hp=7df3b1e3921730c6f8f56b34f4019b2a2894d56a;hpb=d348a943e77ed72dd809cecf03365552545382b2;p=u-boot

diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 7df3b1e392..9758323433 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -75,6 +75,9 @@
 #define ESAI_FIFO_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00063000)
 #define WDOG_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00065000)
 #define I2C1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00066000)
+#define I2C2_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00067000)
+#define I2C3_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000E6000)
+#define I2C4_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000E7000)
 #define WKUP_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006A000)
 #define CCM_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006B000)
 #define GPC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006C000)
@@ -145,7 +148,7 @@
 #define DDRMC_CR18_TCKE(v)				((v) & 0x7)
 #define DDRMC_CR20_AP_EN				(1 << 24)
 #define DDRMC_CR21_TRCD_INT(v)				(((v) & 0xff) << 16)
-#define DDRMC_CR21_TRAS_LOCKOUT				(1 << 8)
+#define DDRMC_CR21_TRAS_LOCKOUT(v)			((v) << 8)
 #define DDRMC_CR21_CCMAP_EN				1
 #define DDRMC_CR22_TDAL(v)				(((v) & 0x3f) << 16)
 #define DDRMC_CR23_BSTLEN(v)				(((v) & 0x7) << 24)
@@ -197,8 +200,8 @@
 #define DDRMC_CR78_BUR_ON_FLY_BIT(v)			((v) & 0xf)
 #define DDRMC_CR79_CTLUPD_AREF(v)			(((v) & 0x1) << 24)
 #define DDRMC_CR82_INT_MASK				0x10000000
-#define DDRMC_CR87_ODT_WR_MAPCS0			(1 << 24)
-#define DDRMC_CR87_ODT_RD_MAPCS0			(1 << 16)
+#define DDRMC_CR87_ODT_WR_MAPCS0(v)			((v) << 24)
+#define DDRMC_CR87_ODT_RD_MAPCS0(v)			((v) << 16)
 #define DDRMC_CR88_TODTL_CMD(v)				(((v) & 0x1f) << 16)
 #define DDRMC_CR89_AODT_RWSMCS(v)			((v) & 0xf)
 #define DDRMC_CR91_R2W_SMCSDL(v)			(((v) & 0x7) << 16)