X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Fcache.h;h=fac65d8d7c9cc36fe6ed4c608eee5584586ddd06;hb=6e2941d787819ae1221d7f8295fa67d2ba94a913;hp=a836e9f2ab2838807d0a53c801b8c5f722eb5b76;hpb=fcfddfd50472d7ce84ef4e2853242bbeb7b37325;p=u-boot

diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index a836e9f2ab..fac65d8d7c 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -16,6 +16,9 @@
 /*
  * Invalidate L2 Cache using co-proc instruction
  */
+#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+void invalidate_l2_cache(void);
+#else
 static inline void invalidate_l2_cache(void)
 {
 	unsigned int val=0;
@@ -24,6 +27,9 @@ static inline void invalidate_l2_cache(void)
 		: : "r" (val) : "cc");
 	isb();
 }
+#endif
+
+int check_cache_range(unsigned long start, unsigned long stop);
 
 void l2_cache_enable(void);
 void l2_cache_disable(void);
@@ -37,14 +43,11 @@ void dram_bank_mmu_setup(int bank);
 #endif
 
 /*
- * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
- * use that value for aligning DMA buffers unless the board config has specified
- * an alternate cache line size.
+ * The value of the largest data cache relevant to DMA operations shall be set
+ * for us in CONFIG_SYS_CACHELINE_SIZE.  In some cases this may be a larger
+ * value than found in the L1 cache but this is OK to use in terms of
+ * alignment.
  */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
 #define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN	64
-#endif
 
 #endif /* _ASM_CACHE_H */