X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Femif.h;h=d9d521a51505728eff9e04674516aba66ce3b222;hb=cf04d0326bd1e24909cfe644c0c8676440a915b1;hp=5f11d7b72eae1a8b49705a876806f9357ac78130;hpb=8dc16cf9dd6196d99969d12741df186a61a2f9a3;p=u-boot

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 5f11d7b72e..d9d521a515 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -581,7 +581,6 @@
 	(0xFF << EMIF_SYS_ADDR_SHIFT))
 
 #define EMIF_EXT_PHY_CTRL_TIMING_REG	0x5
-#define EMIF_EXT_PHY_CTRL_CONST_REG	0x13
 
 /* Reg mapping structure */
 struct emif_reg_struct {
@@ -641,7 +640,9 @@ struct emif_reg_struct {
 	u32 emif_ddr_phy_ctrl_2;
 	u32 padding7[12];
 	u32 emif_rd_wr_exec_thresh;
-	u32 padding8[55];
+	u32 padding8[7];
+	u32 emif_ddr_phy_status[21];
+	u32 padding9[27];
 	u32 emif_ddr_ext_phy_ctrl_1;
 	u32 emif_ddr_ext_phy_ctrl_1_shdw;
 	u32 emif_ddr_ext_phy_ctrl_2;
@@ -690,6 +691,9 @@ struct emif_reg_struct {
 	u32 emif_ddr_ext_phy_ctrl_23_shdw;
 	u32 emif_ddr_ext_phy_ctrl_24;
 	u32 emif_ddr_ext_phy_ctrl_24_shdw;
+	u32 padding[22];
+	u32 emif_ddr_fifo_misaligned_clear_1;
+	u32 emif_ddr_fifo_misaligned_clear_2;
 };
 
 struct dmm_lisa_map_regs {
@@ -855,13 +859,10 @@ struct dmm_lisa_map_regs {
 #define DPD_ENABLE	1
 
 /* Maximum delay before Low Power Modes */
-#ifndef CONFIG_OMAP54XX
-#define REG_CS_TIM		0xF
-#else
 #define REG_CS_TIM		0x0
-#endif
-#define REG_SR_TIM		0xF
-#define REG_PD_TIM		0xF
+#define REG_SR_TIM		0x0
+#define REG_PD_TIM		0x0
+
 
 /* EMIF_PWR_MGMT_CTRL register */
 #define EMIF_PWR_MGMT_CTRL (\
@@ -1113,6 +1114,7 @@ struct emif_regs {
 	u32 freq;
 	u32 sdram_config_init;
 	u32 sdram_config;
+	u32 sdram_config2;
 	u32 ref_ctrl;
 	u32 sdram_tim1;
 	u32 sdram_tim2;
@@ -1141,6 +1143,11 @@ struct lpddr2_mr_regs {
 	s8 mr16;
 };
 
+struct read_write_regs {
+	u32 read_reg;
+	u32 write_reg;
+};
+
 /* assert macros */
 #if defined(DEBUG)
 #define emif_assert(c)	({ if (!(c)) for (;;); })
@@ -1169,4 +1176,5 @@ extern u32 *const T_den;
 
 void config_data_eye_leveling_samples(u32 emif_base);
 u32 emif_sdram_type(void);
+const struct read_write_regs *get_bug_regs(u32 *iterations);
 #endif