X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Fomap_common.h;h=c1a70b15d02ecad1846688ce4af0da3cd1fc558e;hb=c2774e6149a6bedb0941deefec84665119e685a4;hp=056affc3fabdccdf6be6a4ec2dd8ea32118fd1dc;hpb=8968b914be7bfd67d179d0395898bd9db67aaad1;p=u-boot diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 056affc3fa..c1a70b15d0 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -145,6 +145,8 @@ struct prcm_regs { u32 cm_ssc_modfreqdiv_dpll_unipro; u32 cm_coreaon_usb_phy1_core_clkctrl; u32 cm_coreaon_usb_phy2_core_clkctrl; + u32 cm_coreaon_usb_phy3_core_clkctrl; + u32 cm_coreaon_l3init_60m_gfclk_clkctrl; /* cm2.core */ u32 cm_coreaon_bandgap_clkctrl; @@ -231,7 +233,9 @@ struct prcm_regs { u32 cm_l3init_ocp2scp1_clkctrl; u32 cm_l3init_ocp2scp3_clkctrl; u32 cm_l3init_usb_otg_ss1_clkctrl; + u32 cm_l3init_usb_otg_ss2_clkctrl; + u32 prm_irqstatus_mpu; u32 prm_irqstatus_mpu_2; /* cm2.l4per */ @@ -319,6 +323,14 @@ struct prcm_regs { u32 prm_vc_cfg_i2c_clk; u32 prm_abbldo_mpu_setup; u32 prm_abbldo_mpu_ctrl; + u32 prm_abbldo_mm_setup; + u32 prm_abbldo_mm_ctrl; + u32 prm_abbldo_iva_setup; + u32 prm_abbldo_iva_ctrl; + u32 prm_abbldo_eve_setup; + u32 prm_abbldo_eve_ctrl; + u32 prm_abbldo_gpu_setup; + u32 prm_abbldo_gpu_ctrl; u32 cm_div_m4_dpll_core; u32 cm_div_m5_dpll_core; @@ -349,6 +361,10 @@ struct prcm_regs { /* IPU */ u32 cm_ipu_clkstctrl; u32 cm_ipu_i2c5_clkctrl; + + /*l3main1 edma*/ + u32 cm_l3main1_tptc1_clkctrl; + u32 cm_l3main1_tptc2_clkctrl; }; struct omap_sys_ctrl_regs { @@ -357,7 +373,6 @@ struct omap_sys_ctrl_regs { u32 control_core_mac_id_0_hi; u32 control_core_mac_id_1_lo; u32 control_core_mac_id_1_hi; - u32 control_std_fuse_opp_vdd_mpu_2; u32 control_phy_power_usb; u32 control_core_mmr_lock1; u32 control_core_mmr_lock2; @@ -436,6 +451,10 @@ struct omap_sys_ctrl_regs { u32 control_emif1_sdram_config_ext; u32 control_emif2_sdram_config_ext; u32 control_wkup_ldovbb_mpu_voltage_ctrl; + u32 control_wkup_ldovbb_mm_voltage_ctrl; + u32 control_wkup_ldovbb_iva_voltage_ctrl; + u32 control_wkup_ldovbb_eve_voltage_ctrl; + u32 control_wkup_ldovbb_gpu_voltage_ctrl; u32 control_smart1nopmio_padconf_0; u32 control_smart1nopmio_padconf_1; u32 control_padconf_mode; @@ -462,6 +481,7 @@ struct omap_sys_ctrl_regs { u32 control_padconf_wkup_base; u32 iodelay_config_base; u32 ctrl_core_sma_sw_0; + u32 ctrl_core_sma_sw_1; }; struct dpll_params { @@ -519,21 +539,41 @@ struct pmic_data { int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); }; +enum { + OPP_LOW, + OPP_NOM, + OPP_OD, + OPP_HIGH, + NUM_OPPS, +}; + /** * struct volts_efuse_data - efuse definition for voltage * @reg: register address for efuse * @reg_bits: Number of bits in a register address, mandatory. */ struct volts_efuse_data { - u32 reg; + u32 reg[NUM_OPPS]; u8 reg_bits; }; struct volts { - u32 value; + u32 value[NUM_OPPS]; u32 addr; struct volts_efuse_data efuse; struct pmic_data *pmic; + + u32 abb_tx_done_mask; +}; + +enum { + VOLT_MPU, + VOLT_CORE, + VOLT_MM, + VOLT_GPU, + VOLT_EVE, + VOLT_IVA, + NUM_VOLT_RAILS, }; struct vcores_data { @@ -560,6 +600,7 @@ extern struct omap_sys_ctrl_regs const omap5_ctrl; extern struct omap_sys_ctrl_regs const dra7xx_ctrl; extern struct pmic_data tps659038; +extern struct pmic_data lp8733; void hw_data_init(void); @@ -575,25 +616,52 @@ void do_enable_clocks(u32 const *clk_domains, u32 const *clk_modules_explicit_en, u8 wait_for_enable); +void do_disable_clocks(u32 const *clk_domains, + u32 const *clk_modules_disable, + u8 wait_for_disable); + void setup_post_dividers(u32 const base, const struct dpll_params *params); u32 omap_ddr_clk(void); u32 get_sys_clk_index(void); void enable_basic_clocks(void); void enable_basic_uboot_clocks(void); + +void enable_usb_clocks(int index); +void disable_usb_clocks(int index); + void scale_vcores(struct vcores_data const *); +int get_voltrail_opp(int rail_offset); u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, u32 txdone, u32 txdone_mask, u32 opp); s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); -void usb_fake_mac_from_die_id(u32 *id); -void usb_set_serial_num_from_die_id(u32 *id); +void omap_die_id_serial(void); +void omap_die_id_get_board_serial(struct tag_serialnr *serialnr); +void omap_die_id_usbethaddr(void); +void omap_die_id_display(void); + void recalibrate_iodelay(void); void omap_smc1(u32 service, u32 val); +/* + * Low-level helper function used when performing secure ROM calls on high- + * security (HS) device variants by doing a specially-formed smc entry. + */ +u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params); +u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params); + +void enable_edma3_clocks(void); +void disable_edma3_clocks(void); + +void omap_die_id(unsigned int *die_id); + +/* Initialize general purpose I2C(0) on the SoC */ +void gpi2c_init(void); + /* ABB */ #define OMAP_ABB_NOMINAL_OPP 0 #define OMAP_ABB_FAST_OPP 1 @@ -672,7 +740,20 @@ static inline u8 is_dra72x(void) /* DRA7XX */ #define DRA752_ES1_0 0x07520100 #define DRA752_ES1_1 0x07520110 +#define DRA752_ES2_0 0x07520200 #define DRA722_ES1_0 0x07220100 +#define DRA722_ES2_0 0x07220200 + +/* + * silicon device type + * Moving to common from cpu.h, since it is shared by various omap devices + */ +#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + /* * SRAM scratch space entries @@ -686,7 +767,11 @@ static inline u8 is_dra72x(void) #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) #define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) #define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24) -#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28) +#ifndef TI_SRAM_SCRATCH_BOARD_EEPROM_START +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28) +#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) +#endif +#define OMAP_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) /* Boot parameters */ #define DEVICE_DATA_OFFSET 0x18