X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Fomap_common.h;h=f98998343eab2746fa573e123dd2ec07de26513c;hb=6e2941d787819ae1221d7f8295fa67d2ba94a913;hp=aef31266ce9e9c386d7d84302beb3b022e7466b7;hpb=4d339a9e8a758889de5da16b562aff5601bb3d8d;p=u-boot

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index aef31266ce..f98998343e 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -145,6 +145,7 @@ struct prcm_regs {
 	u32 cm_ssc_modfreqdiv_dpll_unipro;
 	u32 cm_coreaon_usb_phy1_core_clkctrl;
 	u32 cm_coreaon_usb_phy2_core_clkctrl;
+	u32 cm_coreaon_usb_phy3_core_clkctrl;
 	u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
 
 	/* cm2.core */
@@ -234,6 +235,7 @@ struct prcm_regs {
 	u32 cm_l3init_usb_otg_ss1_clkctrl;
 	u32 cm_l3init_usb_otg_ss2_clkctrl;
 
+	u32 prm_irqstatus_mpu;
 	u32 prm_irqstatus_mpu_2;
 
 	/* cm2.l4per */
@@ -321,6 +323,14 @@ struct prcm_regs {
 	u32 prm_vc_cfg_i2c_clk;
 	u32 prm_abbldo_mpu_setup;
 	u32 prm_abbldo_mpu_ctrl;
+	u32 prm_abbldo_mm_setup;
+	u32 prm_abbldo_mm_ctrl;
+	u32 prm_abbldo_iva_setup;
+	u32 prm_abbldo_iva_ctrl;
+	u32 prm_abbldo_eve_setup;
+	u32 prm_abbldo_eve_ctrl;
+	u32 prm_abbldo_gpu_setup;
+	u32 prm_abbldo_gpu_ctrl;
 
 	u32 cm_div_m4_dpll_core;
 	u32 cm_div_m5_dpll_core;
@@ -363,7 +373,6 @@ struct omap_sys_ctrl_regs {
 	u32 control_core_mac_id_0_hi;
 	u32 control_core_mac_id_1_lo;
 	u32 control_core_mac_id_1_hi;
-	u32 control_std_fuse_opp_vdd_mpu_2;
 	u32 control_phy_power_usb;
 	u32 control_core_mmr_lock1;
 	u32 control_core_mmr_lock2;
@@ -442,6 +451,10 @@ struct omap_sys_ctrl_regs {
 	u32 control_emif1_sdram_config_ext;
 	u32 control_emif2_sdram_config_ext;
 	u32 control_wkup_ldovbb_mpu_voltage_ctrl;
+	u32 control_wkup_ldovbb_mm_voltage_ctrl;
+	u32 control_wkup_ldovbb_iva_voltage_ctrl;
+	u32 control_wkup_ldovbb_eve_voltage_ctrl;
+	u32 control_wkup_ldovbb_gpu_voltage_ctrl;
 	u32 control_smart1nopmio_padconf_0;
 	u32 control_smart1nopmio_padconf_1;
 	u32 control_padconf_mode;
@@ -526,21 +539,41 @@ struct pmic_data {
 	int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
 };
 
+enum {
+	OPP_LOW,
+	OPP_NOM,
+	OPP_OD,
+	OPP_HIGH,
+	NUM_OPPS,
+};
+
 /**
  * struct volts_efuse_data - efuse definition for voltage
  * @reg:	register address for efuse
  * @reg_bits:	Number of bits in a register address, mandatory.
  */
 struct volts_efuse_data {
-	u32 reg;
+	u32 reg[NUM_OPPS];
 	u8 reg_bits;
 };
 
 struct volts {
-	u32 value;
+	u32 value[NUM_OPPS];
 	u32 addr;
 	struct volts_efuse_data efuse;
 	struct pmic_data *pmic;
+
+	u32 abb_tx_done_mask;
+};
+
+enum {
+	VOLT_MPU,
+	VOLT_CORE,
+	VOLT_MM,
+	VOLT_GPU,
+	VOLT_EVE,
+	VOLT_IVA,
+	NUM_VOLT_RAILS,
 };
 
 struct vcores_data {
@@ -567,6 +600,7 @@ extern struct omap_sys_ctrl_regs const omap5_ctrl;
 extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
 
 extern struct pmic_data tps659038;
+extern struct pmic_data lp8733;
 
 void hw_data_init(void);
 
@@ -597,12 +631,15 @@ void enable_usb_clocks(int index);
 void disable_usb_clocks(int index);
 
 void scale_vcores(struct vcores_data const *);
+int get_voltrail_opp(int rail_offset);
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
 void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
 	       u32 txdone, u32 txdone_mask, u32 opp);
 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
 
+struct tag_serialnr;
+
 void omap_die_id_serial(void);
 void omap_die_id_get_board_serial(struct tag_serialnr *serialnr);
 void omap_die_id_usbethaddr(void);
@@ -612,6 +649,13 @@ void recalibrate_iodelay(void);
 
 void omap_smc1(u32 service, u32 val);
 
+/*
+ * Low-level helper function used when performing secure ROM calls on high-
+ * security (HS) device variants by doing a specially-formed smc entry.
+ */
+u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params);
+u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params);
+
 void enable_edma3_clocks(void);
 void disable_edma3_clocks(void);
 
@@ -700,6 +744,18 @@ static inline u8 is_dra72x(void)
 #define DRA752_ES1_1	0x07520110
 #define DRA752_ES2_0	0x07520200
 #define DRA722_ES1_0	0x07220100
+#define DRA722_ES2_0	0x07220200
+
+/*
+ * silicon device type
+ * Moving to common from cpu.h, since it is shared by various omap devices
+ */
+#define DEVICE_MASK         (BIT(8) | BIT(9) | BIT(10))
+#define TST_DEVICE          0x0
+#define EMU_DEVICE          0x1
+#define HS_DEVICE           0x2
+#define GP_DEVICE           0x3
+
 
 /*
  * SRAM scratch space entries
@@ -713,9 +769,11 @@ static inline u8 is_dra72x(void)
 #define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
 #define OMAP_SRAM_SCRATCH_SYS_CTRL	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
 #define OMAP_SRAM_SCRATCH_BOOT_PARAMS	(SRAM_SCRATCH_SPACE_ADDR + 0x24)
-#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
-#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
-#define OMAP_SRAM_SCRATCH_SPACE_END	(OMAP_SRAM_SCRATCH_BOARD_EEPROM_END)
+#ifndef TI_SRAM_SCRATCH_BOARD_EEPROM_START
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#endif
+#define OMAP_SRAM_SCRATCH_SPACE_END	(TI_SRAM_SCRATCH_BOARD_EEPROM_END)
 
 /* Boot parameters */
 #define DEVICE_DATA_OFFSET	0x18