X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Flib%2Fcache-cp15.c;h=0291afa7bd531088f441808e9f9767cceb4d774b;hb=1c6f6a6ef9f3edf38360a204bc62de83a8039df3;hp=8642010a17500cc8675b5ec03f851e1e8ba929bb;hpb=aaf5e825606a70ddc8fca8e366d8c16a6fd3cc7c;p=u-boot

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 8642010a17..0291afa7bd 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -14,11 +14,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void __arm_init_before_mmu(void)
+__weak void arm_init_before_mmu(void)
 {
 }
-void arm_init_before_mmu(void)
-	__attribute__((weak, alias("__arm_init_before_mmu")));
 
 __weak void arm_init_domains(void)
 {
@@ -44,23 +42,20 @@ void set_section_dcache(int section, enum dcache_option option)
 	page_table[section] = value;
 }
 
-void __mmu_page_table_flush(unsigned long start, unsigned long stop)
+__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
 {
 	debug("%s: Warning: not implemented\n", __func__);
 }
 
-void mmu_page_table_flush(unsigned long start, unsigned long stop)
-	__attribute__((weak, alias("__mmu_page_table_flush")));
-
-void mmu_set_region_dcache_behaviour(u32 start, int size,
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option)
 {
 	u32 *page_table = (u32 *)gd->arch.tlb_addr;
-	u32 upto, end;
+	unsigned long upto, end;
 
 	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
 	start = start >> MMU_SECTION_SHIFT;
-	debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
+	debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
 	      option);
 	for (upto = start; upto < end; upto++)
 		set_section_dcache(upto, option);
@@ -74,10 +69,12 @@ __weak void dram_bank_mmu_setup(int bank)
 
 	debug("%s: bank: %d\n", __func__, bank);
 	for (i = bd->bi_dram[bank].start >> 20;
-	     i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
+	     i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20);
 	     i++) {
 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
 		set_section_dcache(i, DCACHE_WRITETHROUGH);
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+		set_section_dcache(i, DCACHE_WRITEALLOC);
 #else
 		set_section_dcache(i, DCACHE_WRITEBACK);
 #endif