X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Flib%2Fcache.c;h=74cfde637c1c433f3f834cdfbdac48b05ff78b6a;hb=97840b5d1fe0960134c3553a9d9d1c1cd1be784d;hp=6cc136aa3c1e6baeddded6fd8c670e62aac23243;hpb=8b485ba12b0defa0c4ed3559789250238f8331a8;p=u-boot

diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 6cc136aa3c..74cfde637c 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -8,44 +8,90 @@
 /* for now: just dummy functions to satisfy the linker */
 
 #include <common.h>
+#include <malloc.h>
 
-void  __flush_cache(unsigned long start, unsigned long size)
+__weak void flush_cache(unsigned long start, unsigned long size)
 {
-#if defined(CONFIG_ARM1136)
-	void arm1136_cache_flush(void);
+#if defined(CONFIG_CPU_ARM1136)
 
-	arm1136_cache_flush();
+#if !defined(CONFIG_SYS_ICACHE_OFF)
+	asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */
 #endif
-#ifdef CONFIG_ARM926EJS
+
+#if !defined(CONFIG_SYS_DCACHE_OFF)
+	asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */
+#endif
+
+#endif /* CONFIG_CPU_ARM1136 */
+
+#ifdef CONFIG_CPU_ARM926EJS
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 	/* test and clean, page 2-23 of arm926ejs manual */
 	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
 	/* disable write buffer as well (page 2-22) */
 	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 #endif
+#endif /* CONFIG_CPU_ARM926EJS */
 	return;
 }
-void  flush_cache(unsigned long start, unsigned long size)
-	__attribute__((weak, alias("__flush_cache")));
 
 /*
  * Default implementation:
  * do a range flush for the entire range
  */
-void	__flush_dcache_all(void)
+__weak void flush_dcache_all(void)
 {
 	flush_cache(0, ~0);
 }
-void	flush_dcache_all(void)
-	__attribute__((weak, alias("__flush_dcache_all")));
-
 
 /*
  * Default implementation of enable_caches()
  * Real implementation should be in platform code
  */
-void __enable_caches(void)
+__weak void enable_caches(void)
 {
 	puts("WARNING: Caches not enabled\n");
 }
-void enable_caches(void)
-	__attribute__((weak, alias("__enable_caches")));
+
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+/*
+ * Reserve one MMU section worth of address space below the malloc() area that
+ * will be mapped uncached.
+ */
+static unsigned long noncached_start;
+static unsigned long noncached_end;
+static unsigned long noncached_next;
+
+void noncached_init(void)
+{
+	phys_addr_t start, end;
+	size_t size;
+
+	end = ALIGN(mem_malloc_start, MMU_SECTION_SIZE) - MMU_SECTION_SIZE;
+	size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
+	start = end - size;
+
+	debug("mapping memory %pa-%pa non-cached\n", &start, &end);
+
+	noncached_start = start;
+	noncached_end = end;
+	noncached_next = start;
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+	mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
+#endif
+}
+
+phys_addr_t noncached_alloc(size_t size, size_t align)
+{
+	phys_addr_t next = ALIGN(noncached_next, align);
+
+	if (next >= noncached_end || (noncached_end - next) < size)
+		return 0;
+
+	debug("allocated %zu bytes of uncached memory @%pa\n", size, &next);
+	noncached_next = next + size;
+
+	return next;
+}
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */