X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Flib%2Fcache.c;h=b545fb79bc1a185972719b6c5684df6ee3f029e5;hb=5bcc6a8901020ce22a996ef438cfc7be7a0c3995;hp=27123cd121f03c57a03aa4e73e92682dbd7c408c;hpb=4c93da7c392737f2036130c240e2b4bea773d703;p=u-boot

diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 27123cd121..b545fb79bc 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -37,13 +37,31 @@ void  __flush_cache(unsigned long start, unsigned long size)
 	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
 	/* disable write buffer as well (page 2-22) */
 	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif
-#ifdef CONFIG_OMAP34XX
-	void v7_flush_cache_all(void);
-
-	v7_flush_cache_all();
 #endif
 	return;
 }
 void  flush_cache(unsigned long start, unsigned long size)
 	__attribute__((weak, alias("__flush_cache")));
+
+/*
+ * Default implementation:
+ * do a range flush for the entire range
+ */
+void	__flush_dcache_all(void)
+{
+	flush_cache(0, ~0);
+}
+void	flush_dcache_all(void)
+	__attribute__((weak, alias("__flush_dcache_all")));
+
+
+/*
+ * Default implementation of enable_caches()
+ * Real implementation should be in platform code
+ */
+void __enable_caches(void)
+{
+	puts("WARNING: Caches not enabled\n");
+}
+void enable_caches(void)
+	__attribute__((weak, alias("__enable_caches")));