X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Flib%2Frelocate.S;h=475d503dd9df63fda046d225c47205a1bc9c80af;hb=cc4a474873ecf79775bef6b2e73a8b0c7e13b95f;hp=92f531452d5435c1adbfce9d4bc80a0e572cdb3f;hpb=dee332ffb735f65ab922118791a583c17bb0b795;p=u-boot diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index 92f531452d..475d503dd9 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -9,6 +9,9 @@ #include #include #include +#ifdef CONFIG_CPU_V7M +#include +#endif /* * Default/weak exception vectors relocation routine @@ -23,6 +26,15 @@ ENTRY(relocate_vectors) +#ifdef CONFIG_CPU_V7M + /* + * On ARMv7-M we only have to write the new vector address + * to VTOR register. + */ + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + ldr r1, =V7M_SCB_BASE + str r0, [r1, V7M_SCB_VTOR] +#else #ifdef CONFIG_HAS_VBAR /* * If the ARM processor has the security extensions, @@ -46,6 +58,7 @@ ENTRY(relocate_vectors) stmia r1!, {r2-r8,r10} ldmia r0!, {r2-r8,r10} stmia r1!, {r2-r8,r10} +#endif #endif bx lr