X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-keystone%2Fclock-k2e.c;h=7d163a4b1ab99c193f82236ff1faafd850d4d7fe;hb=fc04b923541d984b1544056fd3bfa8129d4e5aac;hp=42092e1060dfce095487f83bd73e578e03525013;hpb=7b50e1599f4e6551a3348ca5f061a596f6f6896e;p=u-boot

diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c
index 42092e1060..7d163a4b1a 100644
--- a/arch/arm/mach-keystone/clock-k2e.c
+++ b/arch/arm/mach-keystone/clock-k2e.c
@@ -11,12 +11,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
-const struct keystone_pll_regs keystone_pll_regs[] = {
-	[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
-	[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
-	[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
@@ -49,7 +43,7 @@ static unsigned long pll_freq_get(int pll)
 			reg = KS2_PASSPLLCTL0;
 			break;
 		case DDR3_PLL:
-			ret = external_clk[ddr3_clk];
+			ret = external_clk[ddr3a_clk];
 			reg = KS2_DDR3APLLCTL0;
 			break;
 		default: