X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-orion5x%2Flowlevel_init.S;h=3f38f36ff29457c6dc97f3a507e2d5068e27e702;hb=595af9db2422fa5ae734cfe615415b17a5098f34;hp=4dacc296e41aa3dea563c92fd385f64b35d26424;hpb=e1cc4d31f889428a4ca73120951389c756404184;p=u-boot

diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S
index 4dacc296e4..3f38f36ff2 100644
--- a/arch/arm/mach-orion5x/lowlevel_init.S
+++ b/arch/arm/mach-orion5x/lowlevel_init.S
@@ -62,14 +62,16 @@
 /*
  * Low-level init happens right after start.S has switched to SVC32,
  * flushed and disabled caches and disabled MMU. We're still running
- * from the boot chip select, so the first thing we should do is set
- * up RAM for us to relocate into.
+ * from the boot chip select, so the first thing SPL should do is to
+ * set up the RAM to copy U-Boot into.
  */
 
 .globl lowlevel_init
 
 lowlevel_init:
 
+#ifdef CONFIG_SPL_BUILD
+
 	/* Use 'r4 as the base for internal register accesses */
 	ldr	r4, =ORION5X_REGS_PHY_BASE
 
@@ -273,5 +275,13 @@ lowlevel_init:
 	orr	r2, r2, r6
 	str	r2, [r3, #0x484]
 
-	/* Return to U-boot via saved link register */
+	/* enable for 2 GB DDR; detection should find out real amount */
+	sub	r6, r6, r6
+	str	r6, [r3, #0x500]
+	ldr	r6, =0x7fff0001
+	str	r6, [r3, #0x504]
+
+#endif /* CONFIG_SPL_BUILD */
+
+	/* Return to U-Boot via saved link register */
 	mov	pc, lr