X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-socfpga%2FKconfig;h=e4cc468e723a963c2e7f90f53b0d0f6a967bc1cc;hb=c17736c02a5704cc48c9d48ce8f0c97e8a66924a;hp=1a441ff4ad38112fbbf8c01640f6bb8a7f5e45d2;hpb=cd9b73177100598e7be0a9033a4a2ed4a7d24fbb;p=u-boot

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 1a441ff4ad..e4cc468e72 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -18,21 +18,49 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
 	bool "Altera SOCFPGA SoCDK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_DENX_MCVEVK
+	bool "DENX MCVEVK (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_EBV_SOCRATES
+	bool "EBV SoCrates (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_DE0_NANO
+	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
+config TARGET_SOCFPGA_TERASIC_SOCKIT
+	bool "Terasic SoCkit (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 endchoice
 
 config SYS_BOARD
-	default "socfpga" if TARGET_SOCFPGA_ARRIA5_SOCDK
-	default "socfpga" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
+	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
 config SYS_SOC
 	default "socfpga"
 
 config SYS_CONFIG_NAME
-	default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK
-	default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
+	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 
 endif