X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-socfpga%2Freset_manager.c;h=b6beaa2f220439a1f5d1c66a1780d2087a4c5f2a;hb=850f788709cef8f7d53d571aec3bfb73b14c5531;hp=1186358a71a3259715173ad95ac4fb74a656db70;hpb=3191611a05df993826a0d2d0d5607e5e38365cce;p=u-boot

diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 1186358a71..b6beaa2f22 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -7,13 +7,16 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/reset_manager.h>
 #include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static const struct socfpga_reset_manager *reset_manager_base =
 		(void *)SOCFPGA_RSTMGR_ADDRESS;
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 /* Assert or de-assert SoCFPGA reset manager reset. */
 void socfpga_per_reset(u32 reset, int set)
@@ -97,6 +100,9 @@ void socfpga_bridges_reset(int enable)
 		/* brdmodrst */
 		writel(0xffffffff, &reset_manager_base->brg_mod_reset);
 	} else {
+		writel(0, &sysmgr_regs->iswgrp_handoff[0]);
+		writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
+
 		/* Check signal from FPGA. */
 		if (!fpgamgr_test_fpga_ready()) {
 			/* FPGA not ready, do nothing. */