X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-socfpga%2Freset_manager.c;h=b6beaa2f220439a1f5d1c66a1780d2087a4c5f2a;hb=850f788709cef8f7d53d571aec3bfb73b14c5531;hp=18af25ced1ae2311aca0e5b73e1c36b479b833eb;hpb=a71df7aa4fa775199280bba19072bd232cc35cb1;p=u-boot diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index 18af25ced1..b6beaa2f22 100644 --- a/arch/arm/mach-socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c @@ -7,13 +7,16 @@ #include #include -#include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_reset_manager *reset_manager_base = (void *)SOCFPGA_RSTMGR_ADDRESS; +static struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; /* Assert or de-assert SoCFPGA reset manager reset. */ void socfpga_per_reset(u32 reset, int set) @@ -39,6 +42,19 @@ void socfpga_per_reset(u32 reset, int set) clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); } +/* + * Assert reset on every peripheral but L4WD0. + * Watchdog must be kept intact to prevent glitches + * and/or hangs. + */ +void socfpga_per_reset_all(void) +{ + const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)); + + writel(~l4wd0, &reset_manager_base->per_mod_reset); + writel(0xffffffff, &reset_manager_base->per2_mod_reset); +} + /* * Write the reset manager register to cause reset */ @@ -84,11 +100,14 @@ void socfpga_bridges_reset(int enable) /* brdmodrst */ writel(0xffffffff, &reset_manager_base->brg_mod_reset); } else { + writel(0, &sysmgr_regs->iswgrp_handoff[0]); + writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]); + /* Check signal from FPGA. */ - if (fpgamgr_poll_fpga_ready()) { - /* FPGA not ready. Wait for watchdog timeout. */ - printf("%s: fpga not ready, hanging.\n", __func__); - hang(); + if (!fpgamgr_test_fpga_ready()) { + /* FPGA not ready, do nothing. */ + printf("%s: FPGA not ready, aborting.\n", __func__); + return; } /* brdmodrst */