X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-socfpga%2Freset_manager.c;h=b6beaa2f220439a1f5d1c66a1780d2087a4c5f2a;hb=850f788709cef8f7d53d571aec3bfb73b14c5531;hp=452377c44afd94d50b0ece40aa2f4426954bc75a;hpb=bdfc2ef64a4df550a4090c31dae9a133c92ac5ca;p=u-boot

diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 452377c44a..b6beaa2f22 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -7,13 +7,16 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/reset_manager.h>
 #include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static const struct socfpga_reset_manager *reset_manager_base =
 		(void *)SOCFPGA_RSTMGR_ADDRESS;
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 /* Assert or de-assert SoCFPGA reset manager reset. */
 void socfpga_per_reset(u32 reset, int set)
@@ -39,14 +42,17 @@ void socfpga_per_reset(u32 reset, int set)
 		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
 }
 
-/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
-void socfpga_watchdog_reset(void)
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
 {
-	/* assert reset for watchdog */
-	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
 
-	/* deassert watchdog from reset (watchdog in not running state) */
-	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
+	writel(~l4wd0, &reset_manager_base->per_mod_reset);
+	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
 }
 
 /*
@@ -94,11 +100,14 @@ void socfpga_bridges_reset(int enable)
 		/* brdmodrst */
 		writel(0xffffffff, &reset_manager_base->brg_mod_reset);
 	} else {
+		writel(0, &sysmgr_regs->iswgrp_handoff[0]);
+		writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
+
 		/* Check signal from FPGA. */
-		if (fpgamgr_poll_fpga_ready()) {
-			/* FPGA not ready. Wait for watchdog timeout. */
-			printf("%s: fpga not ready, hanging.\n", __func__);
-			hang();
+		if (!fpgamgr_test_fpga_ready()) {
+			/* FPGA not ready, do nothing. */
+			printf("%s: FPGA not ready, aborting.\n", __func__);
+			return;
 		}
 
 		/* brdmodrst */
@@ -109,43 +118,3 @@ void socfpga_bridges_reset(int enable)
 	}
 }
 #endif
-
-/* Change the reset state for EMAC 0 and EMAC 1 */
-void socfpga_emac_reset(int enable)
-{
-	if (enable) {
-		socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
-		socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
-	} else {
-#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
-		socfpga_per_reset(SOCFPGA_RESET(EMAC0), 0);
-#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
-		socfpga_per_reset(SOCFPGA_RESET(EMAC1), 0);
-#endif
-	}
-}
-
-/* SPI Master enable (its held in reset by the preloader) */
-void socfpga_spim_enable(void)
-{
-	socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
-	socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
-}
-
-/* Bring UART0 out of reset. */
-void socfpga_uart0_enable(void)
-{
-	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
-}
-
-/* Bring SDRAM controller out of reset. */
-void socfpga_sdram_enable(void)
-{
-	socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
-}
-
-/* Bring OSC1 timer out of reset. */
-void socfpga_osc1timer_enable(void)
-{
-	socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
-}