X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-stm32%2Fstm32f4%2Fclock.c;h=15fcadbbe6fa162b728c19e7e7ae32415ff9fdcf;hb=97c20932361124782cd28ec2028601d04b43ce1e;hp=576d3e68ae4e759a2c9ea0462c309a3fa4114870;hpb=595af9db2422fa5ae734cfe615415b17a5098f34;p=u-boot

diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c
index 576d3e68ae..15fcadbbe6 100644
--- a/arch/arm/mach-stm32/stm32f4/clock.c
+++ b/arch/arm/mach-stm32/stm32f4/clock.c
@@ -66,10 +66,20 @@
 #define PWR_CR_VOS_SCALE_MODE_2	(PWR_CR_VOS1)
 #define PWR_CR_VOS_SCALE_MODE_3	(PWR_CR_VOS0)
 
-#define FLASH_ACR_WS(n)		n
-#define FLASH_ACR_PRFTEN	(1 << 8)
-#define FLASH_ACR_ICEN		(1 << 9)
-#define FLASH_ACR_DCEN		(1 << 10)
+/*
+ * RCC GPIO specific definitions
+ */
+#define RCC_ENR_GPIO_A_EN	(1 << 0)
+#define RCC_ENR_GPIO_B_EN	(1 << 1)
+#define RCC_ENR_GPIO_C_EN	(1 << 2)
+#define RCC_ENR_GPIO_D_EN	(1 << 3)
+#define RCC_ENR_GPIO_E_EN	(1 << 4)
+#define RCC_ENR_GPIO_F_EN	(1 << 5)
+#define RCC_ENR_GPIO_G_EN	(1 << 6)
+#define RCC_ENR_GPIO_H_EN	(1 << 7)
+#define RCC_ENR_GPIO_I_EN	(1 << 8)
+#define RCC_ENR_GPIO_J_EN	(1 << 9)
+#define RCC_ENR_GPIO_K_EN	(1 << 10)
 
 struct pll_psc {
 	u8	pll_m;
@@ -166,10 +176,7 @@ int configure_clocks(void)
 	while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
 		;
 
-	/* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
-	writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
-		| FLASH_ACR_DCEN, &STM32_FLASH->acr);
-
+	stm32_flash_latency_cfg(5);
 	clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
 	setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
 
@@ -237,6 +244,39 @@ void clock_setup(int peripheral)
 	case USART1_CLOCK_CFG:
 		setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);
 		break;
+	case GPIO_A_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN);
+		break;
+	case GPIO_B_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN);
+		break;
+	case GPIO_C_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN);
+		break;
+	case GPIO_D_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN);
+		break;
+	case GPIO_E_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN);
+		break;
+	case GPIO_F_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN);
+		break;
+	case GPIO_G_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN);
+		break;
+	case GPIO_H_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN);
+		break;
+	case GPIO_I_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN);
+		break;
+	case GPIO_J_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN);
+		break;
+	case GPIO_K_CLOCK_CFG:
+		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN);
+		break;
 	default:
 		break;
 	}