X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-tegra%2Fboard.c;h=8c8927d5919ab54c59b5b2d2495dffbbbd631c73;hb=a85670e40da1ef4f299effb73c36e48d39d50106;hp=0ebaf1932556f58d102277fec54f694390bcacd0;hpb=73c38934daa10b518b20f2d21298fc8a8226843b;p=u-boot diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 0ebaf19325..8c8927d591 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -1,11 +1,14 @@ /* - * (C) Copyright 2010-2014 + * (C) Copyright 2010-2015 * NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include +#include #include #include #include @@ -17,6 +20,8 @@ #include #include +void save_boot_params_ret(void); + DECLARE_GLOBAL_DATA_PTR; enum { @@ -29,6 +34,21 @@ enum { UART_COUNT = 5, }; +static bool from_spl __attribute__ ((section(".data"))); + +#ifndef CONFIG_SPL_BUILD +void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) +{ + from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL; + save_boot_params_ret(); +} +#endif + +bool spl_was_boot_source(void) +{ + return from_spl; +} + #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) #if !defined(CONFIG_TEGRA124) #error tegra_cpu_is_non_secure has only been validated on Tegra124 @@ -48,10 +68,11 @@ bool tegra_cpu_is_non_secure(void) #endif /* Read the RAM size directly from the memory controller */ -unsigned int query_sdram_size(void) +static phys_size_t query_sdram_size(void) { struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE; - u32 emem_cfg, size_bytes; + u32 emem_cfg; + phys_size_t size_bytes; emem_cfg = readl(&mc->mc_emem_cfg); #if defined(CONFIG_TEGRA20) @@ -59,6 +80,7 @@ unsigned int query_sdram_size(void) size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024); #else debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg); +#ifndef CONFIG_PHYS_64BIT /* * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits * and will wrap. Clip the reported size to the maximum that a 32-bit @@ -66,9 +88,12 @@ unsigned int query_sdram_size(void) */ if (emem_cfg >= 4096) { size_bytes = U32_MAX & ~(0x1000 - 1); - } else { + } else +#endif + { /* RAM size EMC is programmed to. */ - size_bytes = emem_cfg * 1024 * 1024; + size_bytes = (phys_size_t)emem_cfg * 1024 * 1024; +#ifndef CONFIG_ARM64 /* * If all RAM fits within 32-bits, it can be accessed without * LPAE, so go test the RAM size. Otherwise, we can't access @@ -79,6 +104,7 @@ unsigned int query_sdram_size(void) if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024)) size_bytes = get_ram_size((void *)PHYS_SDRAM_1, size_bytes); +#endif } #endif @@ -98,14 +124,6 @@ int dram_init(void) return 0; } -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - printf("Board: %s\n", sysinfo.board_string); - return 0; -} -#endif /* CONFIG_DISPLAY_BOARDINFO */ - static int uart_configs[] = { #if defined(CONFIG_TEGRA20) #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) @@ -133,12 +151,18 @@ static int uart_configs[] = { -1, FUNCMUX_UART4_GMI, /* UARTD */ -1, -#else /* Tegra124 */ +#elif defined(CONFIG_TEGRA124) FUNCMUX_UART1_KBC, /* UARTA */ -1, -1, FUNCMUX_UART4_GPIO, /* UARTD */ -1, +#else /* Tegra210 */ + FUNCMUX_UART1_UART1, /* UARTA */ + -1, + -1, + FUNCMUX_UART4_UART4, /* UARTD */ + -1, #endif }; @@ -190,7 +214,19 @@ void board_init_uart_f(void) setup_uarts(uart_ids); } -#ifndef CONFIG_SYS_DCACHE_OFF +#if CONFIG_IS_ENABLED(DM_SERIAL) && !CONFIG_IS_ENABLED(OF_CONTROL) +static struct ns16550_platdata ns16550_com1_pdata = { + .base = CONFIG_SYS_NS16550_COM1, + .reg_shift = 2, + .clock = CONFIG_SYS_NS16550_CLK, +}; + +U_BOOT_DEVICE(ns16550_com1) = { + "ns16550_serial", &ns16550_com1_pdata +}; +#endif + +#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */