X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-tegra%2Fcpu.c;h=a3ebb57f20b2d33bc7a57c0f4e39b36fadfe95fc;hb=cd85bec36d0e0d16fedb00e0c434ed070a9c6b37;hp=f7d45e8f6536921a657c2b124622e27557513605;hpb=7a1af7a79bd79ded6a78d0c1afdbc3353669e313;p=u-boot
diff --git a/arch/arm/mach-tegra/cpu.c b/arch/arm/mach-tegra/cpu.c
index f7d45e8f65..a3ebb57f20 100644
--- a/arch/arm/mach-tegra/cpu.c
+++ b/arch/arm/mach-tegra/cpu.c
@@ -1,17 +1,7 @@
/*
* Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see .
+ * SPDX-License-Identifier: GPL-2.0
*/
#include
@@ -67,6 +57,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
},
/*
* T25: 1.2 GHz
@@ -83,6 +75,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
},
/*
* T30: 600 MHz
@@ -99,6 +93,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
{ .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
+ { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
},
/*
* T114: 700 MHz
@@ -114,6 +110,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
+ { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
+ { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
},
/*
@@ -130,6 +128,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
+ { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
+ { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
},
/*
@@ -146,6 +146,8 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
+ { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
+ { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
},
};
@@ -169,6 +171,7 @@ static inline void pllx_set_iddq(void)
int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
u32 divp, u32 cpcon)
{
+ struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
int chip = tegra_get_chip();
u32 reg;
debug("%s entry\n", __func__);
@@ -182,17 +185,21 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
pllx_set_iddq();
/* Set BYPASS, m, n and p to PLLX_BASE */
- reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
- reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
+ reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
+ reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
writel(reg, &pll->pll_base);
/* Set cpcon to PLLX_MISC */
if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
- reg = (cpcon << PLL_CPCON_SHIFT);
+ reg = (cpcon << pllinfo->kcp_shift);
else
reg = 0;
- /* Set dccon to PLLX_MISC if freq > 600MHz */
+ /*
+ * TODO(twarren@nvidia.com) Check which SoCs use DCCON
+ * and add to pllinfo table if needed!
+ */
+ /* Set dccon to PLLX_MISC if freq > 600MHz */
if (divn > 600)
reg |= (1 << PLL_DCCON_SHIFT);
writel(reg, &pll->pll_misc);
@@ -203,9 +210,10 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
writel(reg, &pll->pll_base);
debug("%s: base = 0x%08X\n", __func__, reg);
- /* Set lock_enable to PLLX_MISC */
+ /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
reg = readl(&pll->pll_misc);
- reg |= PLL_LOCK_ENABLE_MASK;
+ if (pllinfo->lock_ena < 32)
+ reg |= (1 << pllinfo->lock_ena);
writel(reg, &pll->pll_misc);
debug("%s: misc = 0x%08X\n", __func__, reg);