X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-tegra%2Fcpu.h;h=1154f8b37ef84b998b886dcf3dbd79304ee35546;hb=c93adc08f393bc401c5929e1045d72dfbea3e126;hp=b4ca44fce18a71288a0197dbf35f06e0e2b708cb;hpb=09f455dca74973ef5e42311162c8dff7e83d44a2;p=u-boot

diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h
index b4ca44fce1..1154f8b37e 100644
--- a/arch/arm/mach-tegra/cpu.h
+++ b/arch/arm/mach-tegra/cpu.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2014
+ * (C) Copyright 2010-2015
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -14,9 +14,9 @@
 #define NVBL_PLLP_KHZ	216000
 #define CSITE_KHZ	144000
 #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
-	defined(CONFIG_TEGRA124)
+	defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
 #define NVBL_PLLP_KHZ	408000
-#define CSITE_KHZ	204000
+#define CSITE_KHZ	136000
 #else
 #error "Unknown Tegra chip!"
 #endif
@@ -35,7 +35,7 @@
 #define PG_UP_TAG_0_PID_CPU	0x55555555	/* CPU aka "a9" aka "mpcore" */
 #define PG_UP_TAG_0             0x0
 
-#define CORESIGHT_UNLOCK	0xC5ACCE55;
+#define CORESIGHT_UNLOCK	0xC5ACCE55
 
 #define EXCEP_VECTOR_CPU_RESET_VECTOR	(NV_PA_EVP_BASE + 0x100)
 #define CSITE_CPU_DBG0_LAR		(NV_PA_CSITE_BASE + 0x10FB0)
@@ -53,6 +53,10 @@
 
 #define SIMPLE_PLLX     (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
 
+/* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */
+#define SB_AA64_RESET_LOW	0x6000C230
+#define SB_AA64_RESET_HIGH	0x6000C234
+
 struct clk_pll_table {
 	u16	n;
 	u16	m;