X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-uniphier%2Fclk%2Fpll-base-ld20.c;h=385f54dfc3b9941fcacabd62fc283f9c011d4e95;hb=87f3dee22b174aa32db8213a3187aa809859c9e2;hp=45fdf0a3226c376066b64d5cfb803f00f733305f;hpb=c30c44e799e1f7d5184c487809edbd612705ba5c;p=u-boot

diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
index 45fdf0a322..385f54dfc3 100644
--- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
@@ -5,8 +5,10 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
+#include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
@@ -18,7 +20,6 @@
 #define SC_PLLCTRL_SSC_EN		BIT(31)
 #define SC_PLLCTRL2_NRSTDS		BIT(28)
 #define SC_PLLCTRL2_SSC_JK_MASK		GENMASK(26, 0)
-#define SC_PLLCTRL3_REGI_SHIFT		16
 #define SC_PLLCTRL3_REGI_MASK		GENMASK(19, 16)
 
 /* PLL type: VPLL27 */
@@ -41,13 +42,16 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
 	if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
 		tmp = readl(base);	/* SSCPLLCTRL */
 		tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
-		tmp |= (487 * freq * ssc_rate / divn / 512) &
-							SC_PLLCTRL_SSC_DK_MASK;
+		tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK,
+				  DIV_ROUND_CLOSEST(487UL * freq * ssc_rate,
+						    divn * 512));
 		writel(tmp, base);
 
 		tmp = readl(base + 4);
 		tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
-		tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK;
+		tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK,
+				  DIV_ROUND_CLOSEST(21431887UL * freq,
+						    divn * 512));
 		writel(tmp, base + 4);
 
 		udelay(50);
@@ -91,7 +95,7 @@ int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
 
 	tmp = readl(base + 8);	/* SSCPLLCTRL3 */
 	tmp &= ~SC_PLLCTRL3_REGI_MASK;
-	tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
+	tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi);
 	writel(tmp, base + 8);
 
 	iounmap(base);