X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-uniphier%2Fclk%2Fpll-ld11.c;h=1a7ec295252408a9aca747334c49fdb9af7e83ad;hb=87f3dee22b174aa32db8213a3187aa809859c9e2;hp=8a4a748cfdb240c3f04ccb975a578380c9c7aa92;hpb=201c9d884dcadb4e76981c30e9915f73de2d09b5;p=u-boot

diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c
index 8a4a748cfd..1a7ec29525 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld11.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c
@@ -4,13 +4,24 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
+#include <linux/delay.h>
 #include <linux/io.h>
 
 #include "../init.h"
 #include "../sc64-regs.h"
 #include "pll.h"
 
+/* PLL type: SSC */
+#define SC_CPLLCTRL	(SC_BASE_ADDR | 0x1400)	/* CPU/ARM */
+#define SC_SPLLCTRL	(SC_BASE_ADDR | 0x1410)	/* misc */
+#define SC_MPLLCTRL	(SC_BASE_ADDR | 0x1430)	/* DSP */
+#define SC_VSPLLCTRL	(SC_BASE_ADDR | 0x1440)	/* Video codec, VPE etc. */
+#define SC_DPLLCTRL	(SC_BASE_ADDR | 0x1460)	/* DDR memory */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL	(SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL	(SC_BASE_ADDR | 0x1520)
+
 void uniphier_ld11_pll_init(void)
 {
 	uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2);	/* 2000MHz -> 1960MHz */
@@ -18,11 +29,14 @@ void uniphier_ld11_pll_init(void)
 	uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2);	/* 1500MHz -> 1600MHz */
 	uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
 
+	uniphier_ld20_sscpll_set_regi(SC_MPLLCTRL, 5);
+
 	mdelay(1);
 
 	uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
 	uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
 	uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL);
+	uniphier_ld20_sscpll_ssc_en(SC_DPLLCTRL);
 
 	uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
 	uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);