X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-uniphier%2Fclk%2Fpll-ld11.c;h=1a7ec295252408a9aca747334c49fdb9af7e83ad;hb=87f3dee22b174aa32db8213a3187aa809859c9e2;hp=b4a97d21610f1027f3b30b7a85eb50a9866a9cd2;hpb=546197b98629fa66a125f87a2b7b61cb8bec6c39;p=u-boot

diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c
index b4a97d2161..1a7ec29525 100644
--- a/arch/arm/mach-uniphier/clk/pll-ld11.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c
@@ -11,6 +11,17 @@
 #include "../sc64-regs.h"
 #include "pll.h"
 
+/* PLL type: SSC */
+#define SC_CPLLCTRL	(SC_BASE_ADDR | 0x1400)	/* CPU/ARM */
+#define SC_SPLLCTRL	(SC_BASE_ADDR | 0x1410)	/* misc */
+#define SC_MPLLCTRL	(SC_BASE_ADDR | 0x1430)	/* DSP */
+#define SC_VSPLLCTRL	(SC_BASE_ADDR | 0x1440)	/* Video codec, VPE etc. */
+#define SC_DPLLCTRL	(SC_BASE_ADDR | 0x1460)	/* DDR memory */
+
+/* PLL type: VPLL27 */
+#define SC_VPLL27FCTRL	(SC_BASE_ADDR | 0x1500)
+#define SC_VPLL27ACTRL	(SC_BASE_ADDR | 0x1520)
+
 void uniphier_ld11_pll_init(void)
 {
 	uniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2);	/* 2000MHz -> 1960MHz */