X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Farm%2Fmach-uniphier%2Fdram_init.c;h=489366c63f948ad36d7f2531c774cb927f82fb7a;hb=b58d3512442357cb023bce69f55c08b9fd21beaa;hp=815f2433f38287eeb7b42d97178743780cf8e9eb;hpb=40345e9ea74b0caef06f205364bb2cf93528cc40;p=u-boot diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 815f2433f3..489366c63f 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -6,8 +6,12 @@ #include #include +#include #include +#include "init.h" +#include "soc-info.h" + DECLARE_GLOBAL_DATA_PTR; static const void *get_memory_reg_prop(const void *fdt, int *lenp) @@ -40,8 +44,7 @@ int dram_init(void) val += ac; - gd->ram_size = sc == 2 ? fdt64_to_cpu(*(fdt64_t *)val) : - fdt32_to_cpu(*val); + gd->ram_size = fdtdec_get_number(val, sc); debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size); @@ -71,11 +74,9 @@ void dram_init_banksize(void) for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells; i++, len -= cells) { - gd->bd->bi_dram[i].start = ac == 2 ? - fdt64_to_cpu(*(fdt64_t *)val) : fdt32_to_cpu(*val); + gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac); val += ac; - gd->bd->bi_dram[i].size = sc == 2 ? - fdt64_to_cpu(*(fdt64_t *)val) : fdt32_to_cpu(*val); + gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc); val += sc; debug("DRAM bank %d: start = %08lx, size = %08lx\n", @@ -83,3 +84,40 @@ void dram_init_banksize(void) (unsigned long)gd->bd->bi_dram[i].size); } } + +#ifdef CONFIG_OF_BOARD_SETUP +/* + * The DRAM PHY requires 64 byte scratch area in each DRAM channel + * for its dynamic PHY training feature. + */ +int ft_board_setup(void *fdt, bd_t *bd) +{ + const struct uniphier_board_data *param; + unsigned long rsv_addr; + const unsigned long rsv_size = 64; + int ch, ret; + + if (uniphier_get_soc_type() != SOC_UNIPHIER_LD20) + return 0; + + param = uniphier_get_board_param(); + if (!param) { + printf("failed to get board parameter\n"); + return -ENODEV; + } + + for (ch = 0; ch < param->dram_nr_ch; ch++) { + rsv_addr = param->dram_ch[ch].base + param->dram_ch[ch].size; + rsv_addr -= rsv_size; + + ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size); + if (ret) + return -ENOSPC; + + printf(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n", + rsv_addr, rsv_size); + } + + return 0; +} +#endif