X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fblackfin%2Fcpu%2FMakefile;h=0a72ec5df3c0d6cb17edc8f43b75cd8e04dda761;hb=9e97834867f496fde45d921a1d3fe213a6e8c7cd;hp=211b8d5450b9b7088ab3dea337cf4705bf2b0e88;hpb=83653121d7382fccfe329cb732f77f116341ef1d;p=u-boot

diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile
index 211b8d5450..0a72ec5df3 100644
--- a/arch/blackfin/cpu/Makefile
+++ b/arch/blackfin/cpu/Makefile
@@ -11,13 +11,14 @@
 
 include $(TOPDIR)/config.mk
 
-LIB	= $(obj)lib$(CPU).a
+LIB	= $(obj)lib$(CPU).o
 
-EXTRA    :=
+EXTRA    := init.elf
 CEXTRA   := initcode.o
 SEXTRA   := start.o
 SOBJS    := interrupt.o cache.o
 COBJS-y  += cpu.o
+COBJS-y  += gpio.o
 COBJS-y  += interrupts.o
 COBJS-$(CONFIG_JTAG_CONSOLE) += jtag-console.o
 COBJS-y  += os_log.o
@@ -26,10 +27,6 @@ COBJS-y  += serial.o
 COBJS-y  += traps.o
 COBJS-$(CONFIG_HW_WATCHDOG)  += watchdog.o
 
-ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
-COBJS-y  += initcode.o
-endif
-
 SRCS     := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS     := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
 EXTRA    := $(addprefix $(obj),$(EXTRA))
@@ -39,7 +36,7 @@ SEXTRA   := $(addprefix $(obj),$(SEXTRA))
 all:	$(obj).depend $(LIB) $(obj).depend $(EXTRA) $(CEXTRA) $(SEXTRA) check_initcode
 
 $(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
 
 $(OBJS): $(obj)bootrom-asm-offsets.h
 $(obj)bootrom-asm-offsets.c: bootrom-asm-offsets.c.in bootrom-asm-offsets.awk
@@ -63,6 +60,11 @@ ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
 	fi
 endif
 
+$(obj)init.lds: init.lds.S
+	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P $^ -o $@
+$(obj)init.elf: $(obj)init.lds $(obj)init.o $(obj)initcode.o
+	$(LD) $(LDFLAGS) -T $^ -o $@
+
 #########################################################################
 
 # defines $(obj).depend target