X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fblackfin%2Fcpu%2Finitcode.c;h=ffaf1017d7b7772f2b0aa25133ae572e5646bd23;hb=3f4978c713255c8406875fbdf23ffed1129bc44b;hp=078209fc246b1404c1f497ea7367429e437168bf;hpb=e9a389a18477c1c57a0b30e9ea8f4d38c6e26e63;p=u-boot

diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c
index 078209fc24..ffaf1017d7 100644
--- a/arch/blackfin/cpu/initcode.c
+++ b/arch/blackfin/cpu/initcode.c
@@ -16,10 +16,9 @@
 #include <asm/mach-common/bits/watchdog.h>
 #include <asm/mach-common/bits/bootrom.h>
 #include <asm/mach-common/bits/core.h>
+#include <asm/serial.h>
 
-#define BUG() while (1) { asm volatile("emuexcpt;"); }
-
-#include "serial.h"
+#define BUG() while (1) asm volatile("emuexcpt;");
 
 #ifndef __ADSPBF60x__
 #include <asm/mach-common/bits/ebiu.h>
@@ -459,15 +458,23 @@ program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
 	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
 		serial_putc('e');
 #ifdef __ADSPBF60x__
+		/* Reset system event controller */
 		bfin_write_SEC_GCTL(0x2);
+		bfin_write_SEC_CCTL(0x2);
 		SSYNC();
+
+		/* Enable fault event input and system reset action in fault
+		 * controller. Route watchdog timeout event to fault interface.
+		 */
 		bfin_write_SEC_FCTL(0xc1);
+		/* Enable watchdog interrupt source */
 		bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
-
-		bfin_write_SEC_CCTL(0x2);
 		SSYNC();
+
+		/* Enable system event controller */
 		bfin_write_SEC_GCTL(0x1);
 		bfin_write_SEC_CCTL(0x1);
+		SSYNC();
 #endif
 		bfin_write_WDOG_CTL(WDDIS);
 		SSYNC();