X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fm68k%2Fcpu%2Fmcf5445x%2Finterrupts.c;h=a2cf51933ae917704dd420fb7d498384197642c0;hb=2b05593da61555b091ee1640dc6c4fcb235771e9;hp=85828a67b5f93f732b6bfb9cb4b5ddc4b95e6bde;hpb=a4145534851bf74619cb373a942613a74547bb82;p=u-boot

diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c
index 85828a67b5..a2cf51933a 100644
--- a/arch/m68k/cpu/mcf5445x/interrupts.c
+++ b/arch/m68k/cpu/mcf5445x/interrupts.c
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,14 +28,15 @@
 /* CPU specific interrupt routine */
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
-	intp->imrh0 |= 0xFFFFFFFF;
-	intp->imrl0 |= 0xFFFFFFFF;
+	setbits_be32(&intp->imrh0, 0xffffffff);
+	setbits_be32(&intp->imrl0, 0xffffffff);
 
 	enable_interrupts();
 	return 0;
@@ -44,9 +45,9 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-	intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
+	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif