X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fmicroblaze%2Fcpu%2Fcache.c;h=ce066b96e99321fe62567cdf59ecde53e09937a5;hb=3c47f2f4871c345c20b9d986b11fec550ef6cc9f;hp=3b7c4d4f7f9a61b79a0dc1cde5b778e5aab12b3d;hpb=83653121d7382fccfe329cb732f77f116341ef1d;p=u-boot

diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index 3b7c4d4f7f..ce066b96e9 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -50,6 +50,8 @@ void	icache_enable (void) {
 }
 
 void	icache_disable(void) {
+	/* we are not generate ICACHE size -> flush whole cache */
+	flush_cache(0, 32768);
 	MSRCLR(0x20);
 }
 
@@ -58,5 +60,26 @@ void	dcache_enable (void) {
 }
 
 void	dcache_disable(void) {
+#ifdef XILINX_USE_DCACHE
+	flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
+#endif
 	MSRCLR(0x80);
 }
+
+void flush_cache (ulong addr, ulong size)
+{
+	int i;
+	for (i = 0; i < size; i += 4)
+		asm volatile (
+#ifdef CONFIG_ICACHE
+				"wic	%0, r0;"
+#endif
+				"nop;"
+#ifdef CONFIG_DCACHE
+				"wdc.flush	%0, r0;"
+#endif
+				"nop;"
+				:
+				: "r" (addr + i)
+				: "memory");
+}