X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fmicroblaze%2Fcpu%2Fstart.S;h=3da711d4d500449866d2464e96f0edf9d1baf45f;hb=3c47f2f4871c345c20b9d986b11fec550ef6cc9f;hp=9077f742ce20ca47f9cf7099ede8b15fba99d609;hpb=c52575350fd6e794717f6bee4f81dbb8038fe22e;p=u-boot

diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 9077f742ce..3da711d4d5 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -108,7 +108,6 @@ _start:
 	sh	r6, r0, r8
 #endif
 
-#ifdef CONFIG_SYS_INTC_0
 	/* interrupt_handler */
 	swi	r2, r0, 0x10	/* interrupt - imm opcode */
 	swi	r3, r0, 0x14	/* interrupt - brai opcode */
@@ -120,7 +119,6 @@ _start:
 	sh	r7, r0, r8
 	rsubi	r8, r10, 0x16
 	sh	r6, r0, r8
-#endif
 
 	/* hardware exception */
 	swi	r2, r0, 0x20	/* hardware exception - imm opcode */
@@ -134,6 +132,12 @@ _start:
 	rsubi	r8, r10, 0x26
 	sh	r6, r0, r8
 
+	/* Flush cache before enable cache */
+	addik	r5, r0, 0
+	addik	r6, r0, XILINX_DCACHE_BYTE_SIZE
+flush:	bralid r15, flush_cache
+	nop
+
 	/* enable instruction and data cache */
 	mfs	r12, rmsr
 	ori	r12, r12, 0xa0
@@ -151,7 +155,7 @@ clear_bss:
 	cmp     r6, r5, r4 /* check if we have reach the end */
 	bnei    r6, 2b
 3:	/* jumping to board_init */
-	brai	board_init
+	brai	board_init_f
 1:	bri	1b
 
 /*