X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fmips%2Fcpu%2Fmips32%2Fcache.S;h=64dfad026324fc573d0b4a17965792826acec3e6;hb=d6bc7dcc0347765c4621c253ea68b07985d8c1f0;hp=e683e8be8cb9e8b42c1f53ac300fafea7672bdff;hpb=3f0675d1a532dbf1fd906103e4b61a6fb842c257;p=u-boot

diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index e683e8be8c..64dfad0263 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -85,17 +85,17 @@ LEAF(mips_init_icache)
 	/* clear tag to invalidate */
 	PTR_LI		t0, INDEX_BASE
 	PTR_ADDU	t1, t0, a1
-1:	cache_op	Index_Store_Tag_I t0
+1:	cache_op	INDEX_STORE_TAG_I t0
 	PTR_ADDU	t0, a2
 	bne		t0, t1, 1b
 	/* fill once, so data field parity is correct */
 	PTR_LI		t0, INDEX_BASE
-2:	cache_op	Fill t0
+2:	cache_op	FILL t0
 	PTR_ADDU	t0, a2
 	bne		t0, t1, 2b
 	/* invalidate again - prudent but not strictly neccessary */
 	PTR_LI		t0, INDEX_BASE
-1:	cache_op	Index_Store_Tag_I t0
+1:	cache_op	INDEX_STORE_TAG_I t0
 	PTR_ADDU	t0, a2
 	bne		t0, t1, 1b
 9:	jr		ra
@@ -110,7 +110,7 @@ LEAF(mips_init_dcache)
 	/* clear all tags */
 	PTR_LI		t0, INDEX_BASE
 	PTR_ADDU	t1, t0, a1
-1:	cache_op	Index_Store_Tag_D t0
+1:	cache_op	INDEX_STORE_TAG_D t0
 	PTR_ADDU	t0, a2
 	bne		t0, t1, 1b
 	/* load from each line (in cached space) */
@@ -120,7 +120,7 @@ LEAF(mips_init_dcache)
 	bne		t0, t1, 2b
 	/* clear all tags */
 	PTR_LI		t0, INDEX_BASE
-1:	cache_op	Index_Store_Tag_D t0
+1:	cache_op	INDEX_STORE_TAG_D t0
 	PTR_ADDU	t0, a2
 	bne		t0, t1, 1b
 9:	jr		ra