X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fmips%2Fcpu%2Fmips32%2Fstart.S;h=3b5b622abedf06ffba3534692d7fba027569ed52;hb=f1c64a08106db5ce87b6afe76785e2d4fddcff63;hp=699c59a7d859e52a19ffccd2904863cea01722f5;hpb=ab0d002677185e6a1bcaf92f507d140b96bb1053;p=u-boot

diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 699c59a7d8..3b5b622abe 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -23,6 +23,7 @@
 
 #ifdef CONFIG_32BIT
 # define MIPS_RELOC	3
+# define STATUS_SET	0
 #endif
 
 #ifdef CONFIG_64BIT
@@ -34,6 +35,7 @@
 	((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
 # endif
 # define MIPS_RELOC	MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
+# define STATUS_SET	ST0_KX
 #endif
 
 	/*
@@ -120,7 +122,7 @@ reset:
 	/* WP(Watch Pending), SW0/1 should be cleared */
 	mtc0	zero, CP0_CAUSE
 
-	setup_c0_status 0 0
+	setup_c0_status STATUS_SET 0
 
 	/* Init Timer */
 	mtc0	zero, CP0_COUNT