X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fmips%2Fcpu%2Fmips32%2Fstart.S;h=70ad198cc9d2a54888d447a8641345bc5faa491a;hb=748bde608a8dfea5b64e186af4d9c27642fe7813;hp=b08a897af0f302df56a3c9463e467902e7e536dd;hpb=1a4596601fd395f3afb8f82f3f840c5e00bdd57a;p=u-boot

diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index b08a897af0..70ad198cc9 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -41,7 +41,7 @@ _start:
 	 nop
 
 	.org 0x10
-#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
+#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
 	/*
 	 * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
 	 * access external NOR flashes. If the board boots from NOR flash the
@@ -51,6 +51,12 @@ _start:
 	 */
 	.word CONFIG_SYS_XWAY_EBU_BOOTCFG
 	.word 0x0
+#elif defined(CONFIG_QEMU_MALTA)
+	/*
+	 * Linux expects the Board ID here.
+	 */
+	.word 0x00000420	# 0x420 (Malta Board with CoreLV)
+	.word 0x00000000
 #endif
 
 	.org 0x200
@@ -199,19 +205,19 @@ in_ram:
 	 * generated by GNU ld. Skip these reserved entries from relocation.
 	 */
 	lw	t3, -4(t0)		# t3 <-- num_got_entries
-	lw	t4, -8(t0)		# t4 <-- _GLOBAL_OFFSET_TABLE_
-	add	t4, s1			# t4 now holds relocated _G_O_T_
-	addi	t4, t4, 8		# skipping first two entries
+	lw	t8, -8(t0)		# t8 <-- _GLOBAL_OFFSET_TABLE_
+	add	t8, s1			# t8 now holds relocated _G_O_T_
+	addi	t8, t8, 8		# skipping first two entries
 	li	t2, 2
 1:
-	lw	t1, 0(t4)
+	lw	t1, 0(t8)
 	beqz	t1, 2f
 	 add	t1, s1
-	sw	t1, 0(t4)
+	sw	t1, 0(t8)
 2:
 	addi	t2, 1
 	blt	t2, t3, 1b
-	 addi	t4, 4
+	 addi	t8, 4
 
 	/* Update dynamic relocations */
 	lw	t1, -16(t0)		# t1 <-- __rel_dyn_start
@@ -221,19 +227,19 @@ in_ram:
 	 addi	t1, 8
 
 1:
-	lw	t3, -4(t1)		# t3 <-- relocation info
+	lw	t8, -4(t1)		# t8 <-- relocation info
 
-	sub	t3, 3
-	bnez	t3, 2f			# skip non R_MIPS_REL32 entries
+	li	t3, 3
+	bne	t8, t3, 2f		# skip non R_MIPS_REL32 entries
 	 nop
 
 	lw	t3, -8(t1)		# t3 <-- location to fix up in FLASH
 
-	lw	t4, 0(t3)		# t4 <-- original pointer
-	add	t4, s1			# t4 <-- adjusted pointer
+	lw	t8, 0(t3)		# t8 <-- original pointer
+	add	t8, s1			# t8 <-- adjusted pointer
 
 	add	t3, s1			# t3 <-- location to fix up in RAM
-	sw	t4, 0(t3)
+	sw	t8, 0(t3)
 
 2:
 	blt	t1, t2, 1b