X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fmips%2Finclude%2Fasm%2Finca-ip.h;h=5f03e2aa20194ac3bff0b54192a538d3b1e22b36;hb=ec9b386e267bf9bf0b0214836458adca502a64c3;hp=e787a1dee656906fc29712fd7bd1ba74aa06e9c4;hpb=83653121d7382fccfe329cb732f77f116341ef1d;p=u-boot

diff --git a/arch/mips/include/asm/inca-ip.h b/arch/mips/include/asm/inca-ip.h
index e787a1dee6..5f03e2aa20 100644
--- a/arch/mips/include/asm/inca-ip.h
+++ b/arch/mips/include/asm/inca-ip.h
@@ -1,4 +1,3 @@
-
 /******************************************************************************
        Copyright (c) 2002, Infineon Technologies.  All rights reserved.
 
@@ -894,12 +893,7 @@
 /*  Module      :  EBU register address and bits                       */
 /***********************************************************************/
 
-#if defined(CONFIG_INCA_IP)
 #define INCA_IP_EBU                          (0xB8000200)
-#elif defined(CONFIG_PURPLE)
-#define INCA_IP_EBU                          (0xB800D800)
-#endif
-
 /***********************************************************************/
 
 
@@ -1495,12 +1489,7 @@ If set and clear bit are written concurrently with 1, the associated bit is not
 /*  Module      :  ASC register address and bits                       */
 /***********************************************************************/
 
-#if defined(CONFIG_INCA_IP)
 #define INCA_IP_ASC                          (0xB8000400)
-#elif defined(CONFIG_PURPLE)
-#define INCA_IP_ASC                          (0xBE500000)
-#endif
-
 /***********************************************************************/