X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc5xxx%2Fstart.S;h=517b5808fecf00f65091d4d1736cfb0e2d5e6f01;hb=06d513ecb61a6711157707ebe10b968aacc0f2a8;hp=92858fce3a4e600f91f88632ad4cc27716e44e22;hpb=083d506937002f2795c80fe0c3ae194ad2c3d085;p=u-boot

diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S
index 92858fce3a..517b5808fe 100644
--- a/arch/powerpc/cpu/mpc5xxx/start.S
+++ b/arch/powerpc/cpu/mpc5xxx/start.S
@@ -3,31 +3,15 @@
  *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  *  Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /*
  *  U-Boot - Startup Code for MPC5xxx CPUs
  */
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc5xxx.h>
-#include <timestamp.h>
 #include <version.h>
 
 #define CONFIG_MPC5xxx 1	/* needed for Linux kernel header files */
@@ -40,10 +24,6 @@
 #include <asm/mmu.h>
 #include <asm/u-boot.h>
 
-#ifndef  CONFIG_IDENT_STRING
-#define  CONFIG_IDENT_STRING ""
-#endif
-
 /* We don't want the  MMU yet.
 */
 #undef	MSR_KERNEL
@@ -54,6 +34,7 @@
 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Set up GOT: Global Offset Table
  *
@@ -69,9 +50,10 @@
 	GOT_ENTRY(transfer_to_handler)
 
 	GOT_ENTRY(__init_end)
-	GOT_ENTRY(_end)
+	GOT_ENTRY(__bss_end)
 	GOT_ENTRY(__bss_start)
 	END_GOT
+#endif
 
 /*
  * Version string
@@ -79,9 +61,7 @@
 	.data
 	.globl	version_string
 version_string:
-	.ascii U_BOOT_VERSION
-	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
-	.ascii CONFIG_IDENT_STRING, "\0"
+	.ascii U_BOOT_VERSION_STRING, "\0"
 
 /*
  * Exception vectors
@@ -90,6 +70,18 @@ version_string:
 	. = EXC_OFF_SYS_RESET
 	.globl	_start
 _start:
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	/*
+	 * This is the entry of the real U-Boot from a board port
+	 * that supports SPL booting on the MPC5200. We only need
+	 * to call board_init_f() here. Everything else has already
+	 * been done in the SPL u-boot version.
+	 */
+	GET_GOT			/* initialize GOT access		*/
+	bl	board_init_f	/* run 1st part of board init code (in Flash)*/
+	/* NOTREACHED - board_init_f() does not return */
+#else
 	mfmsr	r5			/* save msr contents		*/
 
 	/* Move CSBoot and adjust instruction pointer                   */
@@ -158,7 +150,9 @@ lowboot_reentry:
 	/* Be careful to keep code relocatable !			*/
 	/*--------------------------------------------------------------*/
 
+#ifndef CONFIG_SPL_BUILD
 	GET_GOT			/* initialize GOT access		*/
+#endif
 
 	/* r3: IMMR */
 	bl	cpu_init_f	/* run low-level CPU init code (in Flash)*/
@@ -166,7 +160,9 @@ lowboot_reentry:
 	bl	board_init_f	/* run 1st part of board init code (in Flash)*/
 
 	/* NOTREACHED - board_init_f() does not return */
+#endif
 
+#ifndef CONFIG_SPL_BUILD
 /*
  * Vector Table
  */
@@ -339,6 +335,7 @@ int_return:
 	lwz	r1,GPR1(r1)
 	SYNC
 	rfi
+#endif /* CONFIG_SPL_BUILD */
 
 /*
  * This code initialises the MPC5xxx processor core
@@ -528,6 +525,7 @@ get_pvr:
 	mfspr	r3, PVR
 	blr
 
+#ifndef CONFIG_SPL_BUILD
 /*------------------------------------------------------------------------------*/
 
 /*
@@ -670,7 +668,7 @@ in_ram:
 	lwzux	r0,r4,r11
 	cmpwi	r0,0
 	add	r0,r0,r11
-	stw	r10,0(r3)
+	stw	r4,0(r3)
 	beq-	5f
 	stw	r0,0(r4)
 5:	bdnz	3b
@@ -680,7 +678,7 @@ clear_bss:
 	 * Now clear BSS segment
 	 */
 	lwz	r3,GOT(__bss_start)
-	lwz	r4,GOT(_end)
+	lwz	r4,GOT(__bss_end)
 
 	cmplw	0, r3, r4
 	beq	6f
@@ -765,3 +763,5 @@ trap_init:
 
 	mtlr	r4			/* restore link register    */
 	blr
+
+#endif /* CONFIG_SPL_BUILD */