X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc83xx%2Fserdes.c;h=a0bc477dc3c401f09e20ed309f12ffc05f37d1d8;hb=52c411805c090999f015df8bdf8016fb684746d0;hp=64033fe4c35dec86b046f6f745ba122d0bc7fc65;hpb=500fbae2043532275e09a8666d837d052c9bad9a;p=u-boot

diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c
index 64033fe4c3..a0bc477dc3 100644
--- a/arch/powerpc/cpu/mpc83xx/serdes.c
+++ b/arch/powerpc/cpu/mpc83xx/serdes.c
@@ -1,25 +1,26 @@
 /*
  * Freescale SerDes initialization routine
  *
- * Copyright (C) 2007 Freescale Semicondutor, Inc.
+ * Copyright 2007,2011 Freescale Semiconductor, Inc.
  * Copyright (C) 2008 MontaVista Software, Inc.
  *
  * Author: Li Yang <leoli@freescale.com>
  *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <config.h>
 #include <common.h>
 #include <asm/io.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
 
 /* SerDes registers */
 #define FSL_SRDSCR0_OFFS		0x0
 #define FSL_SRDSCR0_DPP_1V2		0x00008800
+#define FSL_SRDSCR0_TXEQA_MASK		0x00007000
+#define FSL_SRDSCR0_TXEQA_SATA		0x00001000
+#define FSL_SRDSCR0_TXEQE_MASK		0x00000700
+#define FSL_SRDSCR0_TXEQE_SATA		0x00000100
 #define FSL_SRDSCR1_OFFS		0x4
 #define FSL_SRDSCR1_PLLBW		0x00000040
 #define FSL_SRDSCR2_OFFS		0x8
@@ -71,6 +72,11 @@ void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd)
 		tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;
 		out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
 
+		/* Configure SRDSCR0 */
+		clrsetbits_be32(regs + FSL_SRDSCR0_OFFS,
+			FSL_SRDSCR0_TXEQA_MASK | FSL_SRDSCR0_TXEQE_MASK,
+			FSL_SRDSCR0_TXEQA_SATA | FSL_SRDSCR0_TXEQE_SATA);
+
 		/* Configure SRDSCR1 */
 		tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
 		tmp &= ~FSL_SRDSCR1_PLLBW;