X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=arch%2Fpowerpc%2Fcpu%2Fmpc85xx%2Fb4860_serdes.c;h=a5709dddc009653deabdac1243cdc0e20e0207e9;hb=ceb9190969e458dcd1427566f762dbb9cfdfdc94;hp=c96ad0b486ebca24a8f56b693bedf1cec9483d0d;hpb=5e5097c110ab5d6bda7f18b7a795d17f27ac3d36;p=u-boot

diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index c96ad0b486..a5709dddc0 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -15,9 +15,11 @@ struct serdes_config {
 	u8 lanes[SRDS_MAX_LANES];
 };
 
-#ifdef CONFIG_PPC_B4860
+#ifdef CONFIG_ARCH_B4860
 static struct serdes_config serdes1_cfg_tbl[] = {
 	/* SerDes 1 */
+	{0x01, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x02, {AURORA, AURORA, CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x04, {AURORA, AURORA, CPRI6, CPRI5,
@@ -26,6 +28,8 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x06, {AURORA, AURORA, CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1} },
+	{0x07, {AURORA, AURORA, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x08, {AURORA, AURORA, CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x09, {AURORA, AURORA, CPRI6, CPRI5,
@@ -42,6 +46,8 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 		CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x12, {CPRI8, CPRI7,	CPRI6, CPRI5,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
@@ -50,6 +56,9 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
 	{0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
 		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x2F, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1} },
 	{0x30, {AURORA, AURORA,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		CPRI4, CPRI3, CPRI2, CPRI1}},
@@ -82,12 +91,18 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 };
 static struct serdes_config serdes2_cfg_tbl[] = {
 	/* SerDes 2 */
+	{0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		AURORA, AURORA,	SRIO1, SRIO1} },
 	{0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		AURORA, AURORA,	SRIO1, SRIO1}},
 	{0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		AURORA, AURORA,	SRIO1, SRIO1}},
+	{0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2,
+		AURORA, AURORA, SRIO1, SRIO1} },
 	{0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2,
 		AURORA, AURORA, SRIO1, SRIO1}},
@@ -95,6 +110,9 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 		SRIO2, SRIO2,
 		AURORA, AURORA,
 		SRIO1, SRIO1}},
+	{0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
@@ -107,18 +125,30 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 	{0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x79, {SRIO2, SRIO2, SRIO2, SRIO2,
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
 		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2, AURORA, AURORA,
+		XFI_FM1_MAC9, XFI_FM1_MAC10} },
 	{0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2, AURORA, AURORA,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
 	{0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2, AURORA, AURORA,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10} },
 	{0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SRIO2, SRIO2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x8C, {SRIO2, SRIO2, SRIO2, SRIO2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10} },
 	{0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
@@ -133,6 +163,9 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
 		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+	{0xB1, {PCIE1, PCIE1, PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10} },
 	{0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		XFI_FM1_MAC9, XFI_FM1_MAC10}},
@@ -147,7 +180,7 @@ static struct serdes_config serdes2_cfg_tbl[] = {
 };
 #endif
 
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
 static struct serdes_config serdes1_cfg_tbl[] = {
 	{0x0D, {NONE, NONE, CPRI6, CPRI5,
 		CPRI4, CPRI3, NONE, NONE} },
@@ -155,12 +188,17 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 		CPRI4, CPRI3, NONE, NONE} },
 	{0x0F, {NONE, NONE, CPRI6, CPRI5,
 		CPRI4, CPRI3, NONE, NONE} },
+	{0x17, {NONE, NONE,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		NONE, NONE, NONE, NONE} },
 	{0x18, {NONE, NONE,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		NONE, NONE, NONE, NONE} },
 	{0x1B, {NONE, NONE,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		NONE, NONE, NONE, NONE} },
+	{0x1D, {NONE, NONE, AURORA, AURORA,
+		NONE, NONE, NONE, NONE} },
 	{0x1E, {NONE, NONE, AURORA, AURORA,
 		NONE, NONE, NONE, NONE} },
 	{0x21, {NONE, NONE, AURORA, AURORA,
@@ -170,19 +208,29 @@ static struct serdes_config serdes1_cfg_tbl[] = {
 	{}
 };
 static struct serdes_config serdes2_cfg_tbl[] = {
+	{0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		NONE, NONE, NONE, NONE} },
 	{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		NONE, NONE, NONE, NONE} },
 	{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, AURORA,
 		NONE, NONE, NONE, NONE} },
+	{0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		AURORA, AURORA, NONE, NONE, NONE, NONE} },
 	{0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		AURORA, AURORA,	NONE, NONE, NONE, NONE} },
 	{0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		AURORA, AURORA,	NONE, NONE, NONE, NONE} },
+	{0x99, {PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		NONE, NONE, NONE, NONE} },
 	{0x9A, {PCIE1, PCIE1,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
 		NONE, NONE, NONE, NONE} },
+	{0x9D, {PCIE1, PCIE1, PCIE1, PCIE1,
+		NONE, NONE, NONE, NONE} },
 	{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
 		NONE, NONE, NONE, NONE} },
 	{}